A Digital Receiver Architecture for Bluetooth in 0.25-&lt;formula formulatype="inline"&gt; &lt;tex&gt;$\mu$&lt;/tex&gt;&lt;/formula&gt;m CMOS Technology and Beyond

Neubauer, André; Hammes, M.

doi:10.1109/tcsi.2007.902610

Cited by 4 publications

(4 citation statements)

References 17 publications

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“…Since the DSP block needs no calculation-intensive functions, the implementation complexity can be reduced in comparison with that of the DSP blocks required by conventional digital demodulators [5], [30].…”

Section: Digital Demodulatormentioning

confidence: 99%

“…In order to achieve a low-power GFSK transceiver employing a limiter and a digital demodulator simultaneously in the receiver [5], this paper utilizes a technique of time-to-digital conversion in the digital demodulator [6]- [8] to permit using a preceding limiter. By this arrangement, the goals of low power consumption, low cost, and small size can be achieved while the advantages of the digital demodulator are kept.…”

Section: Introductionmentioning

confidence: 99%

“…the power of the converted baseband noise computed by(5) with that simulated by Matlab. The values of , and are assumed to be 6 MHz, 14 dB, and 1 MHz, respectively.…”

mentioning

confidence: 99%

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A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

Chen¹,

Yang²,

Huang³

et al. 2009

IEEE Trans. Circuits Syst. I

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A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm 2 chip by a 0.18-m CMOS process. The receiver achieves 89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply. Index Terms-Complex bandpass filter, demodulator, frequency synthesizer, low-noise amplifier (LNA), open-loop VCO modulation, time-to-digital converter (TDC).

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Section: Digital Demodulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

Chen¹,

Yang²,

Huang³

et al. 2009

IEEE Trans. Circuits Syst. I

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“…Such efficient designs require a system approach from which each component that constitutes an IoT system will be carefully designed [24], as shown in Figure 1. Current research works in circuits and systems' efficiency mostly focus on the design of efficient protocols or architectures for communication Integrated Circuit (IC) [25][26][27][28], or on more efficient power management systems [29][30][31], but they usually do not include efficient integration of the proposed IC into a comprehensive IoT system. In this way, the design of the front end IC usually aims to meet an impedance of 50 Ω, such that the design of the transmission line and the matching circuit or antenna can be reduced to the choice of components with characteristic impedance equal 50 Ω.…”

Section: Introductionmentioning

confidence: 99%

Internet of Things: A Review on Theory Based Impedance Matching Techniques for Energy Efficient RF Systems

Couraud

Vauché

Daskalakis

et al. 2021

JLPEA

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Within an increasingly connected world, the exponential growth in the deployment of Internet of Things (IoT) applications presents a significant challenge in power and data transfer optimisation. Currently, the maximization of Radio Frequency (RF) system power gain depends on the design of efficient, commercial chips, and on the integration of these chips by using complex RF simulations to verify bespoke configurations. However, even if a standard 50Ω transmitter’s chip has an efficiency of 90%, the overall power efficiency of the RF system can be reduced by 10% if coupled with a standard antenna of 72Ω. Hence, it is necessary for scalable IoT networks to have optimal RF system design for every transceiver: for example, impedance mismatching between a transmitter’s antenna and chip leads to a significant reduction of the corresponding RF system’s overall power efficiency. This work presents a versatile design framework, based on well-known theoretical methods (i.e., transducer gain, power wave approach, transmission line theory), for the optimal design in terms of power delivered to a load of a typical RF system, which consists of an antenna, a matching network, a load (e.g., integrated circuit) and transmission lines which connect all these parts. The aim of this design framework is not only to reduce the computational effort needed for the design and prototyping of power efficient RF systems, but also to increase the accuracy of the analysis, based on the explanatory analysis within our design framework. Simulated and measured results verify the accuracy of this proposed design framework over a 0–4 GHz spectrum. Finally, a case study based on the design of an RF system for Bluetooth applications demonstrates the benefits of this RF design framework.

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Verification of the Integrated Bluetooth Modem

Mohamed

2021

Bluetooth 5.0 Modem Design for IoT Devices

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A Digital Receiver Architecture for Bluetooth in 0.25-<formula formulatype="inline"> <tex>$\mu$</tex></formula>m CMOS Technology and Beyond

Cited by 4 publications

References 17 publications

A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

Internet of Things: A Review on Theory Based Impedance Matching Techniques for Energy Efficient RF Systems

Verification of the Integrated Bluetooth Modem

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