A Digital Polar CMOS Power Amplifier With a 102-dB Power Dynamic Range Using a Digitally Controlled Bias Generator

Choi, Hae-Wook; Lee, Yu‐Mi; Hong, Songcheol

doi:10.1109/tmtt.2014.2298386

Cited by 18 publications

(13 citation statements)

References 24 publications

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“…The cascode combination of class‐D and class‐E with CMOS technology is introduce first moment in this work. From last few years, several studies on the development of CMOS power amplifiers has been introduced whose brief description are follows next. For example, in the study of Koo et al, a fully integrated dual‐mode power amplifier with a back‐off region of 10 dB and very low quiescent current are achieved for practical wireless communication environment.…”

Section: Introductionmentioning

confidence: 99%

“…For example, in the study of Koo et al, a fully integrated dual‐mode power amplifier with a back‐off region of 10 dB and very low quiescent current are achieved for practical wireless communication environment. A digitally controlled bias generator‐based CMOS power amplifier achieved peak output power of 22 dBm for WCDMA . The RF power amplifier with 40% of global efficiency achieved −5 dBm output for autonomous wireless sensor nodes .…”

Section: Introductionmentioning

confidence: 99%

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An integrated cascode DE power amplifier for RF calibration system towards measurement of bio‐sensor applications

Kumar

Kanaujia

Dwari

et al. 2018

Micro & Optical Tech Letters

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The integrated cascode DE power amplifier for RF calibration system toward measurement of bio‐sensor applications is presented in this paper. The proposed architecture includes cascode class‐D and class‐E amplifier stages that could provide better calibration accuracy in terms of wide bandwidth, power efficiency, high gain, minimum group delay, and lowest calibration system. The achieved high performance of proposed amplifier overcomes conventional measurement issues toward bio‐sensor application. The inductive π‐shape matching network drives RF input to class‐D stage and provides wide bandwidth of operation. While class‐E stage with T‐shape matching network maintains stable gain and high efficiency in desired band of operation. The performance of the CMOS proposed amplifier is executed in RF ADS simulator along with fabricated chip using commercial TSMC 65 nm manufacturing process. The simulated and measured data achieves Ku band (12 GHz to 18 GHz) with almost flat gain of 30 dB. The DE amplifier provides an output and saturated power of 17 dBm with highest power efficiency of 45%. The measured calibration factor at maximum resonant frequency of 13.5 GHz achieves best value of less than 2 dB within input power range of −50 dBm to 0 dBm. The lowest calibration factor provides best accuracy along with the other parameters and could be beneficial toward bio‐sensor measurement in the various applications. The calculated area of the fabricated chip is as 0.45*0.45mm2 where class‐E consuming area of 38% and class‐D of 44%. The fabricated chip consumes less power consumption of 3.2 mW under power supply of 1 V.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An integrated cascode DE power amplifier for RF calibration system towards measurement of bio‐sensor applications

Kumar

Kanaujia

Dwari

et al. 2018

Micro & Optical Tech Letters

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“…To extend battery lifetime, it is essential to enhance the efficiency of power amplifiers. Accordingly, many researchers have attempted to improve the efficiency of power amplifiers . The envelope tracking (ET) technique is becoming increasingly popular at present .…”

Section: Introductionmentioning

confidence: 99%

A 2.4‐GHz CMOS power amplifier using a gain and stability enhancement technique for IEEE 802.11N WLAN applications

Lee

Park

2016

Micro & Optical Tech Letters

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In this work, we propose a gain and stability enhancement technique with compact size for RF CMOS linear power amplifier applications. The proposed amplifier is designed with differential and cascode structures. To realize a compact size of the power amplifier, the driver stage is merged into the power stage of the power amplifier. To minimize the number of essentially required inductors, the load impedance of the power stage is shared with the driver stage of the power amplifier. Additionally, to moderate stability problems in the power amplifier, the closed loop is removed using a common‐gate transistor, which operates in the saturation region. The power amplifier can then operate in the linear operation. To prove the feasibility of the proposed linear amplifier, we designed a 2.4 GHz CMOS power amplifier using the 180‐nm RF CMOS process. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2265–2268, 2016

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“…To overcome this problem, various efficiency enhancement techniques have been investigated so far, including Doherty PA, out-phasing PA, digital mode PA, and so on [1]- [3]. However, each configuration has its own disadvantages respectively.…”

mentioning

confidence: 99%

“…Likewise, out-phasing PA suffers from the similar problems due to the reactive compensation components inside the power combiner [2]. The maximum continuous wave (CW) output power of the digital mode PA is limited to 25 dBm [3].…”

mentioning

confidence: 99%

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

Woo

Park

Kim

et al. 2014

IEEE Trans. Microwave Theory Techn.

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In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0. 32-m silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of 33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control.Index Terms-CMOS, dynamic stacking, envelope tracking (ET), long-term evolution (LTE), power amplifier (PA), wideband.

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A Digital Polar CMOS Power Amplifier With a 102-dB Power Dynamic Range Using a Digitally Controlled Bias Generator

Cited by 18 publications

References 24 publications

An integrated cascode DE power amplifier for RF calibration system towards measurement of bio‐sensor applications

An integrated cascode DE power amplifier for RF calibration system towards measurement of bio‐sensor applications

A 2.4‐GHz CMOS power amplifier using a gain and stability enhancement technique for IEEE 802.11N WLAN applications

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

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