A Digital Pixel Sensor Array With Programmable Dynamic Range

Kitchen, A.; Bermak, Amine; Bouzerdoum, A.

doi:10.1109/ted.2005.859698

Cited by 104 publications

(66 citation statements)

References 15 publications

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“…Such predictive ADCs usually involve a pulse modulator, in charge of quantifying in continuous-time the amplitude of the sensor signal at 1 bit, and a digital filter to cut off the high frequency components of the resulting quantification noise and to complete discretization in time. Basically, two different pulse modulation (PM) approaches can be found for the first stage of the ADC: pulse width modulation (PWM) also known as time-to-first-spike [56][57][58][59][60][61][62][63][64], and pulse density modulation (PDM) also called spike-counting [65-68, 62, 69, 70], or even mixed solutions like [71,72]. Each one of these pixel modulation strategies can be performed synchronously by means of traditional frame acquisition times [56,65,[57][58][59][60][61][62] or the more recently introduced event-based approach [63].…”

Section: Fpa Architecturesmentioning

confidence: 99%

“…Basically, two different pulse modulation (PM) approaches can be found for the first stage of the ADC: pulse width modulation (PWM) also known as time-to-first-spike [56][57][58][59][60][61][62][63][64], and pulse density modulation (PDM) also called spike-counting [65-68, 62, 69, 70], or even mixed solutions like [71,72]. Each one of these pixel modulation strategies can be performed synchronously by means of traditional frame acquisition times [56,65,[57][58][59][60][61][62] or the more recently introduced event-based approach [63]. This last scheme was, nonetheless, developed to allow an asynchronous event-driven readout [73,74,68,69,64,70,72] and is commonly exploited in this frame-free scenario.…”

Section: Fpa Architecturesmentioning

confidence: 99%

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Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications

Margarit¹

2017

Springer Theses

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Certifiquen ResumLa present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat.Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació.Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar.L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: viii• Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma.• Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Aquest treball ha cond...

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Section: Fpa Architecturesmentioning

confidence: 99%

Section: Fpa Architecturesmentioning

confidence: 99%

Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications

Margarit¹

2017

Springer Theses

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“…A number of digital pixel solutions can be found in the literature [7][8][9][10][11][12]. The major differences between various implementations are in the type of the photosensor, the way of analog to digital conversion applied, the type of the digital memory, the type of the digital code, the type of the pixel reset, etc.…”

Section: Digital Pixel With Analog Comparatormentioning

confidence: 99%

“…The contrast and brightness of the images have been increased in order to visualize the FPN noise. The given values of FPN have been calculated using the commonly used definition [21]: FPN = σ(∆n)/n max • 100% = σ(∆n)/2 8 • 100%. Simulations have been carried out for various values of mismatch for specific pixel components.…”

Section: The Impact Of Mismatch On Image Non-uniformitymentioning

confidence: 99%

On analog comparators for CMOS digital pixel applications. A comparative study

Jendernalik

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. Voltage comparator is the only -apart from the light-to-voltage converter -analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 µm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based on a very simple non-differential comparator with a reduced size and degraded performance. Theoretical analysis of the comparator nonideality effect on the quality of the image obtained from the digital pixel matrix as well as simulation results are provided.Key words: CMOS image sensor, CMOS digital pixel, analog comparator, fixed pattern noise (FPN). On analog comparators for CMOS digital pixel applications.A comparative study W. JENDERNALIK* Faculty of Electronics Telecommunications and Informatics, Gdańsk University of Technology, 11/12 Narutowicza St., 80-952 Gdańsk, Poland pixels containing a photosensor and a complete A/D converter are larger than 20 µm × 20 µm. This results in degradation of the fill factor, increase of the matrix area, and the increase of the integrated image sensor price. For this reason, development of A/D converter solutions that can be implemented on a small pixel while maintaining sufficiently large bit resolution and high conversion quality becomes of primary importance. One of the most important components of the A/D converter is a CMOS analog voltage comparator. Such a comparator usually consists of a conventional MOS differential pair with a current mirror as an active load, an amplifier stage implemented as a common-source configuration, as well as one or two CMOS inverters which work as an additional amplification stage. The comparator footprint may contribute to as much as 20 to 30 percent of the entire pixel area [7]. In order to reduce the comparator size, one needs to reduce the sizes of its transistors, which leads to degrading the electrical performance of the circuit. Smaller transistor size means larger technological spread of their parameters and the increased offset voltage of the comparator. Moreover, the 1/f noise level is also increased.In this work, we investigate a possibility of applying -in a digital pixel -a simple non-differential analog comparator consisting of four CMOS transistors. Such a comparator is characterized by worse electrical performance compared to a conventional differential comparator; however, it features a considerably smaller footprint. In order to compare the influence of the analog comparator performance on the image quality, two versions of a digital pixel realized in 0.35 µm CMOS technology have been designed. The pixels are only different with respect to the analog comparator. Simulation studies have been performed for the two matrices of the siz...

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“…Two other parameters, namely power consumption and area, become particularly important for circuits with high number of ADCs. The representative examples of such systems are CMOS image sensors (CISs) [10,16,19,20,22], especially massively parallel CISs [5,[11][12][13]15,21]. For the latter, A/D conversion is implemented at the pixel level, as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

Jendernalik

2017

Circuits Syst Signal Process

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This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis shows that power dissipation of a comparator contributes significantly to a total power consumption of an ADC. Thus, minimization of the comparator energy consumption during the analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time comparators operating in the slope ADC, under the same bias conditions, the proposed comparator shows a 2-3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18-μm CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.

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A Digital Pixel Sensor Array With Programmable Dynamic Range

Cited by 104 publications

References 15 publications

Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications

Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications

On analog comparators for CMOS digital pixel applications. A comparative study

An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

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