A digital neuro chip with adaptive segmentation quantizer neuron architecture (ASQA)

Abstract

bstract In this paper, we discuss a chip simulates a neural network. and titomatically generates optiinuin iietwork stnicture according to input data. It handles 28 sub ne~ual networks which coinpose a large scale neural network. By our origiiial rchitecture, iiecessary inernory size to get the same recognition performancc as nnventional chip is reduced to 9%. It classilks up to 16,384 categories and solvcs lrge size prohleins such as Kaiiji recognition oii a single chip. It consists (IC 250K aiisistors on a 6.02 i i i~i i x 7.08 iiiiii chip by 0.5 pili douhle iiictal CMOS tcchnology. . INTRODUCTIONBoth digital aiid analog iieuro chips have been iinpleineiited for a purpose of high )eed neural processing. Coinpared with aiialog iieuro chips: digital chips are inferior processing performance, hut superior in operatioiial accuracy and inass productivity.irtheriiiore, it is easy to iiieiiiorizc syiiaplic wcights in digital chips. Recently dig i t a1 ii cur o chips w i 11-1 i nip 1 ciiicii t at i o ii tcch ii o I og X es s~i c h as riiiil ti 'ocessor architecture 111 1 or [he reduction scheme of the nunibeir of calculation 1211 3. 1 tve been developed, aiid higher performance have been achieved. However, those :uro chips are very expeiisive because large size of Ineinory for syiiaptic wei.ghts id several chips are needed to classify large categories. Optimum network size and m e paraiiieters have to be deteriniiied by trial and error in order to obtain better cognition accuracy with less ineinory size. Additionally, those conventional iieiiro lips are 1101 suitable for pattcrii recognition with a large nuiiibcr of categories. Big iLleS of iinpleineiitatioii of iieuro chip ;UC how to dekrininc an approprialc size ol 7803-3550-3/96$5.00C3 1996 559