A digital cellular-based system for retinal vessel-tree extraction

Resco, Cesar Diaz; Nieto, Alejandro; Osorio, Roberto R.; Brea, V.M.; Vilariño, D.L.

doi:10.1109/ecctd.2009.5275113

Search citation statements

Order By: Relevance

Paper Sections

Select...

Methods1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2011

Publication Types

Select...

Article1

Relationship

Self Cite1

Independent0

Authors

Journals

Cited by 1 publication

(1 citation statement)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…readInt(); px_4 = px_5; px_5=px_6; px_6=in.readInt (); px_7=px_8; px_8=px_9; px_9=in.readInt (); tmp = (-px_1-px_2-px_3); tmp = tmp + (-px_4+8*px_5-px_6); tmp = tmp + (-px_7-px_8-px_9); if (tmp < 0) tmp = 0; out.writeInt(tmp); } More details of the implementation can be found in Resco et al [42].…”

Section: Methodsmentioning

confidence: 99%

Performance analysis of massively parallel embedded hardware architectures for retinal image processing

Nieto

Brea

Vilariño

et al. 2011

J Image Video Proc.

Self Cite

View full text Add to dashboard Cite

This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of lowlevel tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA).

show abstract

Section: Methodsmentioning

confidence: 99%