A Detailed Study on Phase Predictors

Vandeputte, Frederik; Eeckhout, Lieven; Bosschere, Koen De

doi:10.1007/11549468_64

Cited by 16 publications

(18 citation statements)

References 13 publications

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“…Phase detection and prediction mechanisms [17,18,36,42] can help improve DVFS performance prediction accuracy and hence the overall utility of DVFS. Specifically, a DVFS mechanism can benefit from phase prediction by triggering re-training of the DVFS performance predictor in the beginning of each phase, and switching to the predicted optimal operating point for the rest of the phase.…”

Section: Phase Predictionmentioning

confidence: 99%

Predicting Performance Impact of DVFS for Realistic Memory Systems

Miftakhutdinov

Ebrahimi

Patt

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Dynamic voltage and frequency scaling (DVFS) can make modern processors more power and energy efficient if we can accurately predict the effect of frequency scaling on processor performance. State-of-the-art DVFS performance predictors, however, fail to accurately predict performance when confronted with realistic memory systems. We propose CRIT+BW, the first DVFS performance predictor designed for realistic memory systems. In particular, CRIT+BW takes into account both variable memory access latency and performance effects of prefetching. When evaluated with a realistic memory system, DVFS realizes 65% of potential energy savings when using CRIT+BW, compared to less than 34% when using previously proposed DVFS performance predictors.

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Section: Phase Predictionmentioning

confidence: 99%

Predicting Performance Impact of DVFS for Realistic Memory Systems

Miftakhutdinov

Ebrahimi

Patt

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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“…In the second case, the scenario prediction point may be moved to an earlier point in time by augmenting the prediction function with a mechanism that selects from the possible set of scenarios predicted by the function, the one with highest probability. For example, the mechanism may use advanced phase predictors [Vandeputte et al 2005]. Using the probabilistic approach, the miss-prediction may increase.…”

Section: Predictionmentioning

confidence: 99%

“…At the end of each instruction interval, the hardware predicts if the running scenario will continue for at least one more interval or if the program will switch to another scenario during the next interval. For this prediction, we use a Markov-based predictor [Vandeputte et al 2005]. If a scenario switch is predicted, the configuration of the processor is adapted to the energy-optimal hardware configuration of the predicted scenario.…”

Section: High Performance Processor Adaptationmentioning

confidence: 99%

System-scenario-based design of dynamic embedded systems

Gheorghita

Palkovic²,

Hamers

et al. 2009

ACM Trans. Des. Autom. Electron. Syst.

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131

117

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Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publicationCitation for published version (APA): Gheorghita, S. V., Palkovic, M., Hamers, J., Vandecappelle, A., Mamagkakis, S., Basten, T., ... Bosschere, . System scenario based design of dynamic embedded systems. (ES reports; Vol. 2007-06). Eindhoven: Technische Universiteit Eindhoven. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. In the past decade, real-time embedded systems have become much more complex due to the introduction of a lot of new functionality in one application, and due to running multiple applications concurrently. This increases the dynamic nature of today's applications and systems, and tightens the requirements for their constraints in terms of deadlines and energy consumption. State-of-theart design methodologies try to cope with these novel issues by identifying several most used cases and dealing with them separately, reducing the newly introduced complexity. This paper presents a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, which can be utilized by existing design methodologies to increase their efficiency. It is based on the concept of system scenarios, which group system behaviors that are similar from a multi-dimensional cost perspective, such as resource requirements, delay, and energy consumption, in such a way that the system can be configured to exploit this cost similarity. At design-time, these scenarios are individually optimized. Mechanisms for predicting the current scenario at run-time and for switching between scenarios are ...

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“…Thus, these scenarios need to be predicted at run time. In order to do this, Gheorghita et al used the Markov-based predictor developed by Vandeputte et al [10] .…”

Section: Single-user Usage Patternsmentioning

confidence: 99%

Capacity metric for chip heterogeneous multiprocessors

Otoom

Paul

2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMsor Workload Specific Processors (WSPs).For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric.In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity iii surfaces, we are able to identify when a system meets its demands and by how much.Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude.In this work, we make the following major ...

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A Detailed Study on Phase Predictors

Cited by 16 publications

References 13 publications

Predicting Performance Impact of DVFS for Realistic Memory Systems

Predicting Performance Impact of DVFS for Realistic Memory Systems

System-scenario-based design of dynamic embedded systems

Capacity metric for chip heterogeneous multiprocessors

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