A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices

Jeyanthi, J. E.; Samuel, T. S. Arun; Geege, A. Sharon; Vimala, P.

doi:10.1007/s12633-021-01148-7

Cited by 10 publications

(6 citation statements)

References 51 publications

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“…Parasitic capacitances need to be decreased in order to make improvements to the switching speed of TFETs. This parasitic capacitance is modeled as C gd ¼ ∂Q g ∂V ds , Where Q g is the charges accumulated in the channel and it is obtained from Equation (8). Gate to drain capacitance (C gd ) of the proposed SiGe/Si Fe HPD DG TFET is compared with Si-DG TFET, Si-Fe-DG TFET, and Si-Ge-Fe-DG TFET.…”

Section: Resultsmentioning

confidence: 99%

“…However, because of the broad and indirect bandgap, the typical silicon-based TFET has an incredibly low ON-state current (I ON ), limiting its practical deployment. [6][7][8] Another critical disadvantage of TFETs is their ambipolar conductivity. Many studies 9,10 have been extensively researched with line tunneling, which involves aligning the gate-induced electric field with the BTBT current to boost the TFET's I ON current.…”

Section: Introductionmentioning

confidence: 99%

“…For TFETs, the current conduction mechanism is band‐to‐band tunneling (BTBT) from the valance band of the source to the channel's conduction band, but for MOSFETs, thermal diffusion of the carriers with energy greater than the channel area barrier is thermal diffusion responsible for the current conduction. However, because of the broad and indirect bandgap, the typical silicon‐based TFET has an incredibly low ON‐state current ( I ON ), limiting its practical deployment 6–8 . Another critical disadvantage of TFETs is their ambipolar conductivity.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Heterostructure performance evaluation: A numerical simulation and analytical modeling of the ferroelectric pocket doped double gate tunnel FET

Jeyanthi,

Samuel,

Song

et al. 2023

Int J Numerical Modelling

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This paper presents a novel 2D analytical model for investigating the influence of the ferroelectric dielectric on the performance of pocket doped double gate tunnel FET. It takes into account the effect of the gate and drain voltages, the thickness of the gate insulator, the capacitance of the gate insulator, and source and drain depletions. The surface potential thus carefully obtained is utilized for calculating lateral electric field, drain current, gate‐to‐drain capacitance, and transconductance. As a result, it has been demonstrated that the result of our model with several device structures matches very well with the data obtained through the technology computer‐aided design (TCAD) simulation. In addition, it has also been shown that the proposed tunnel field‐effect transistors (TFET) structure, which incorporates the ferroelectric dielectric and SiGe/Si heterostructure, has the best ON current, ON/OFF ratio, transconductance, and cut‐off frequency (fT).

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Heterostructure performance evaluation: A numerical simulation and analytical modeling of the ferroelectric pocket doped double gate tunnel FET

Jeyanthi,

Samuel,

Song

et al. 2023

Int J Numerical Modelling

Self Cite

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“…This research focuses on the identification cell lines derived from cancer of breast tissue based on their dielectric constant values, utilizing a Double-Gate Tunnel Field-Effect Transistor (DG-TFET)based device [13,14]. This device employs two nanocavities (NC) and a dual metal gate positioned below the two gate electrodes to increase detecting sensitivity.…”

Section: Introductionmentioning

confidence: 99%

Design and Evaluation of a Double-Gate Tunnel Field Effect Transistor for the Detection of Breast Cancer Cells

Vimala,

Saleem,

Samuel

2024

JBBBE

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This research paper investigates the application of a Double Gate (DG) Tunnel Field-Effect Transistor (DG-TFET) for the detection of cell lines derived from breast cancer tissue, namely Hs578T, MDA-MB-231, MCF-7, and T47D. The device incorporates two nanocavities positioned beneath the two gate electrodes, significantly enhancing detection capabilities. The study emphasizes the differentiation between healthy non-tumorigenic cells (MCF-10A) and breast cancer-derived cell lines by incorporating gate engineering into the TFET. Furthermore, the research explores the impact of changes in dielectric values specific to different breast malignant cell types on the biosensor's detection capabilities. Additionally, the investigation delves into the influence of variations in device geometry, including cavity dimensions and dielectric layer thickness, on critical parameters such as drain current sensitivity, transconductance sensitivity, and ION/IOFF sensitivity. Sensitivity analysis concerns drive current, ION/IOFF ratio, threshold voltage (Vth), and transconductance. The structural design of the device is tailored to facilitate array-based diagnosis and screening of cell lines derived from breast cancer tissue. This design offers several advantages, including a simplified transduction process, compatibility with CMOS processes, cost-effectiveness, reproducibility, and adjustable electrical responses. The researchers employed ATLAS, a two-dimensional (2D) device simulator from Silvaco, to model and define the device structure. The numerical simulations validate the device's performance, demonstrating favorable ON-OFF transition profiles.

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“…In one such investigation, Tunnel field effect transistors (TFETs) came into existence which can produce high switching ratio and steeper subthreshold swing (SS) [5][6][7] . However, Silicon (Si) TFETs with SiO 2 as gate oxide, offer poor electrostatics and experimental results show that the on-state currents in TFETs are typically lower than that of MOSFETs [8][9][10][11] . So, with low on-state current as drawback, new configurations, and materials for TFET are proposed, heterojunction tunnel field effect transistor (HTFET), L and U channel TFETs (LTFET & UTFET) and usage of III-V group materials 12,13 for tunneling devices.…”

mentioning

confidence: 99%

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

Boggarapu

Lakshmi

2023

Sci Rep

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This work is intended to design a quadrature phase shift keying (QPSK) system starting from the device design, characterization and optimization which is then followed by the circuit level implementation and finally the system level configuration. Tunnel Field Effect Transistor (TFET) technology came into existence because of the inability of CMOS (Complementary Metal Oxide Semiconductor) to produce reduced leakage current (Ioff) in the subthreshold regime. With the effects of scaling and requirement of high doping concentrations, TFET is not capable to produce stable reduction in Ioff due to the variation in ON and OFF current. To improve the switching ratio of the current and to obtain good subthreshold swing (SS) by overcoming the limitations of junction TFET, a new device design is proposed for the first time in this work. A pocket double gate asymmetric Junction less TFET (poc-DG-AJLTFET) structure has been proposed in which uniform doping is used to eliminate the junctions and a pocket of length 2 nm made of Silicon–Germanium (SiGe) material has been introduced to improve the designed structure performance in the weak inversion region and increase the drive current (ION). The work function has been tuned to produce the best results for poc-DG-AJLTFET and with our proposed poc-DG-AJLTFET, effects of interface traps are eliminated as against conventional JLTFET structures. The notion that low-threshold voltage device yields high IOFF has been proved wrong with our poc-DG-AJLTFET design, as it produced low threshold voltage with lower IOFF which reduced the power dissipation. Numerical results show that drain induced barrier lowering (DIBL) of 2.75 mV/V is achieved which could be less than 35 times required for short channel effects to be minimum. In terms of gate to drain capacitance (Cgd), it is found that ~ 103 reduction which greatly improves device inertia to internal electrical interference. Also, improvement in transconductance is achieved by 104 times, 103 times improvement in ION/IOFF ratio, and 400 times higher unity gain cutoff-frequency (ft) which would be required by all communication systems. The Verilog models of the designed device are used to construct the leaf cells of quadrature phase shift keying (QPSK) system and the implemented QPSK system is taken as a key evaluator in the performance evaluation in terms of propagation delay and power consumption of poc-DG-AJLTFET in modern satellite communication systems.

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A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices

Cited by 10 publications

References 51 publications

Heterostructure performance evaluation: A numerical simulation and analytical modeling of the ferroelectric pocket doped double gate tunnel FET

Heterostructure performance evaluation: A numerical simulation and analytical modeling of the ferroelectric pocket doped double gate tunnel FET

Design and Evaluation of a Double-Gate Tunnel Field Effect Transistor for the Detection of Breast Cancer Cells

Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications

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