A Detailed Investigation on the Role of Internet of Things (IOT) for Better Model-Driven Processing System Based on User Defined Constraints

Elangovan, P.; Mohseni, Milad; Prasad, P. P. M.; Kanagasabai, N.; Nirmal, Mahesh; Ventayen, Randy Joy Magno

doi:10.1109/icacite53722.2022.9823919

Cited by 1 publication

(1 citation statement)

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“…In addition to EPCM, OPCM cells also wear out with time, which results in reduced endurance. It is the write ability of an OPCM cell that determines its endurance [50]. The COSMOS read operation also includes a reset operation that affects the endurance of the OPCM cells.…”

Section: Lifetimementioning

confidence: 99%

OML-PCM: optical multi-level phase change memory architecture for embedded computing systems

Mohseni,

Novin

2023

Eng. Res. Express

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Unlike Dynamic Random Access Memory (DRAM), Phase Change Memory (PCM) offers higher density, longer data retention, and improved scalability because of its non-volatility and low leakage power. However, Electrically-Addressable PCM (EPCM) has a higher dynamic power and long latency than DRAM. To address these issues, scientists have developed Optically-Addressable PCM (OPCM), which uses 5-level cells instead of 2-level cells in EPCM. A silicon photonic link allows optical signals to reach OPCM cells at a high speed. Hence, OPCM can achieve a higher density while maintaining better performance at multi-level cells and consuming less power per access. However, OPCM is not suitable for general use since the photonic links do not provide an electrical interface to the processor. The aim of this paper is to present a hybrid OPCM architecture based on the use of novel multi-bank clusters with distinctive properties. Electrical-Optical-Electrical conversion (EOE) allows OPCM cells to be randomly accessed by using DRAM-like circuitry. The proposed hybrid design with multi-core processing and OPCM achieves a 2.13x speedup over previous approaches while consuming less Central Processing Unit (CPU) power. It is important to note that the proposed design offers 97 units fewer power-consistent bits than EPCM. In addition, the proposed architecture provides comparable performance and power to DDR4, as well as improved bandwidth density, space efficiency, and versatility. The Gem5 simulator was used to evaluate the design. Based on the outcomes of the analysis, the proposed architecture offers 2.08x and 2.14x better evaluations and density performance than EPCM. Furthermore, the execution time has been reduced by 2.13x, the analysis time by 1.23x, and the composition time by 4.60%.

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Section: Lifetimementioning

confidence: 99%