A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe &amp;#x00026; dual stress liner in SRAM

Khamankar, R.; Bowen, C.; Bu, H.; Corum, D.; Fujii, Ichiro; Gu, Yanfeng; Hornung, B.; Kim, T.; Kirkpatrick, B.; Kirmse, K. H. R.; Krishnan, A.T.; Lin, Chun-Hsiung; Liu, L.; Lowry, Taylor; Montgomery, Christopher B.; Olubuyide, O.O.; Prins, Steven L.; Riley, D. Jason; Yu, Shuai; Blatchford, J. W.; Machala, C.; O’Brien, Christopher J.; Shinn, G.; Grider, T.

doi:10.1109/vlsit.2008.4588608

2008 Symposium on VLSI Technology 2008

DOI: 10.1109/vlsit.2008.4588608

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A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe & dual stress liner in SRAM

R. Khamankar

C. Bowen

H. Bu

et al.

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A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe & dual stress liner in SRAM

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