1995
DOI: 10.1142/s0218001495000134
|View full text |Cite
|
Sign up to set email alerts
|

A Design Methodology for Very Large Array Processors-Part 2: Pacube Vlsi Arrays

Abstract: The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effect… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2

Citation Types

0
4
0

Publication Types

Select...
1

Relationship

1
0

Authors

Journals

citations
Cited by 1 publication
(4 citation statements)
references
References 0 publications
0
4
0
Order By: Relevance
“…Hence as presented in [4] Functional Communication Graph (FCG) for RGGT can be obtained with the help of G-set functions. fig.la, The block diagram of Pacube macrocell architecture is shown in fig.2.…”
Section: Pacube Vlsi Array Based Massively Parallel Architecture For mentioning
confidence: 99%
See 3 more Smart Citations
“…Hence as presented in [4] Functional Communication Graph (FCG) for RGGT can be obtained with the help of G-set functions. fig.la, The block diagram of Pacube macrocell architecture is shown in fig.2.…”
Section: Pacube Vlsi Array Based Massively Parallel Architecture For mentioning
confidence: 99%
“…These G-set functions are evaluated by the method of massive bit array formation and array reduction (addition process) [4]. Massive bit array is partitioned into column domains.…”
Section: Pacube Vlsi Array Based Massively Parallel Architecture For mentioning
confidence: 99%
See 2 more Smart Citations