A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

Safwat, Sally; Ghoneima, Maged; Ismail, Yehea

doi:10.1109/iceac.2011.6136676

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…Among the PLL components, the PFC is key to full digitalization of PLLs, and several devices using numerical values for phase comparison have been reported [28,29]. A time-to-digital converter (TDC) [30] and Bang-bang-type phase comparator [31] are frequently used. Since TDCs have been improved through miniaturization of the semiconductor process, it has been reported that their Fig.…”

Section: Technologies For Future Pll Designmentioning

confidence: 99%

Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications

Kokubo

2023

IEICE Trans. Fundamentals

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This paper summarizes the modulation configurations of phase locked loops (PLLs) and their integration in semiconductor circuits, e.g., the input modulation for cellular phones, directmodulation for low power wireless sensor networks, feedback-loop modulation for high-speed transmission, and two-point modulation for short-range radio transceivers. In this survey, basic configuration examples of integrated circuits for wired and wireless applications which are using the PLL modulation configurations are explained. It is important to select the method for simply and effectively determining the characteristics corresponding to the specific application. The paper also surveys technologies for future PLL design for digitizing of an entire PLL to reduce the phase noise due to a modulation by using a feedback loop with a precise digital phase comparison and a numerically controlled oscillator with high linearity.

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Section: Technologies For Future Pll Designmentioning

confidence: 99%

Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications

Kokubo

2023

IEICE Trans. Fundamentals

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“…To analyze this phenomenon, the nonlinear model presented in [14] is modified as listed in Eqn. (2)(3)(4)(5).…”

Section: Higher Order Adpllmentioning

confidence: 99%

“…However, the design of TDC based all-digital PLL is more complex, the power consumption is higher, and also consumes larger area. The other kind is bangbang detector based all-digital PLLs [3][4][5][6][7][8], which have been widely used in clock synthesis for digital systems and data recovery circuits for high-speed wireline applications. It can be implemented by digital circuits or even using cell-based design flow.…”

Section: Introductionmentioning

confidence: 99%

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO

Chang

Chin

Ibrahim

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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An all-digital phase-locked loop (ADPLL) with adaptive higher-order filter is proposed in this paper. The proposed ADPLL can select the first to third order of the loop filter by turning the IIR filter to adjust the system performance and attenuate input noise. Moreover, the phenomenon that spurious tone is getting closer to the main tone at higher-order ADPLL will be analyzed in this paper. The chip has been designed and implemented in TSMC 40 nm GP 1P10M CMOS process technology. The total area of the ADPLL core is 0.0106 mm2. By turning on the IIR filter, the measured rms jitter is 0.6 ps (0.298 % UI) and the power consumption is 5.1 mW from a 0.9 V supply at 4.96 GHz output frequency with 40 MHz reference clock.

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Design and implementation of a low-area reconfigurable and synthesizable digital loop filter for ADPLL

Ahmad,

Lee

2023

2023 Fourteenth International Conference on Ubiquitous and Future Networks (ICUFN)

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A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

Cited by 4 publications

References 5 publications

Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications

Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO

Design and implementation of a low-area reconfigurable and synthesizable digital loop filter for ADPLL

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