A design for digital, dynamic clock deskew

Dike, C.; Kurd, Nasser; Patra, Priyadarsan; Barkatullah, J.S.

doi:10.1109/vlsic.2003.1221151

Cited by 25 publications

(15 citation statements)

References 5 publications

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“…Alternative topologies are tree and mesh, first proposed in [8]. Their main advantage is that there is no physical reference domain, i.e., SDs are synchronized to each other.…”

Section: Scalability Issuesmentioning

confidence: 99%

Uncertainty in DLL deskewing schemes

Figueiredo

Aguiar

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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This paper proposes an analytical model to evaluate deskewing uncertainty, considering floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains of clock deskewing or finding the best deskewing topology for a given application, at an early design stage. Also, we show that all deskewing schemes trade static for dynamic clock uncertainty and thus, our model can be used to determine the maximum tolerable noise levels if a deskewing scheme is to be applied.

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“…Alternative topologies are tree and mesh, first proposed in [8]. Their main advantage is that there is no physical reference domain, i.e., SDs are synchronized to each other.…”

Section: Scalability Issuesmentioning

confidence: 99%

Uncertainty in DLL deskewing schemes

Figueiredo

Aguiar

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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“…Different clock tree design methods would likely have different results from our experiments. Techniques such as fullcustom layout and deskewing technologies [26] can certainly generate lower skew results but they dramatically increase design effort, may increase area and power consumption, and are not commonly used. For example, active deskewing and scanchain adjustments used for Itanium [27] enable a very large clock tree with skew less than 10 ps, but the clock generation and distribution circuits dissipate approximately 25 W of power.…”

Section: A Auto Generated Clock Trees For Different Sizes Of Chip Mumentioning

confidence: 99%

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Baas

2009

IEEE Trans. VLSI Syst.

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Chip multiprocessors with globally asynchronous locally synchronous (GALS) clocking styles are promising candidates for processing computationally-intensive and energy-constrained workloads. The GALS methodology simplifies clock tree design, provides opportunities to use clock and voltage scaling jointly in system submodules to achieve high energy efficiencies, and can also result in easily scalable clocking systems. However, its use typically also introduces performance penalties due to additional communication latency between clock domains. We show that GALS chip multiprocessors (CMPs) with large inter-processor first-inputs-first-outputs (FIFOs) buffers can inherently hide much of the GALS performance penalty while executing applications that have been mapped with few communication loops. In fact, the penalty can be driven to zero with sufficiently large FIFOs and the removal of multiple-loop communication links. We present an example mesh-connected GALS chip multiprocessor and show it has a less than 1% performance (throughput) reduction on average compared to the corresponding synchronous system for many DSP workloads. Furthermore, adaptive clock and voltage scaling for each processor provides an approximately 40% power savings without any performance reduction. These results compare favorably with the GALS uniprocessor, which compared to the corresponding synchronous uniprocessor, has a reported greater than 10% performance (throughput) reduction and an energy savings of approximately 25% using dynamic clock and voltage scaling for many general purpose applications.Index Terms-Array processor, chip multiprocessor, energy efficient, globally asynchronous locally synchronous (GALS), low power, scalable.

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“…This approach, however, lacks the dynamic tuning capability required to cope with the environment variations. With the third approach presented in [4] and [5], the delay elements are programmed dynamically using phase detectors in a clock distribution network. Using programmable delay elements with phase detectors is potentially effective in reducing the deviations in circuit characteristics induced by both process and environment parameter variations.…”

Section: Previous Workmentioning

confidence: 99%

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Tawfik

Kursun

2007

Proceedings of the 2007 International Symposium on Low Power Electronics and Design

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A methodology based on supply voltage and frequency scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a scaled supply voltage and frequency. The optimum supply voltage that minimizes clock skew is 44% less than the nominal supply voltage in a 0.18μm CMOS technology. Combined frequency multiplier and level converter circuits are utilized at the leaves of the clock tree for restoring the standard full voltage swing clock signal with the higher target clock frequency in order to maintain the performance of the system. A novel dual-threshold-voltage frequency doubler with voltage level conversion capability, suppressed temperature fluctuations sensitivity, and low power consumption characteristics is presented. The temperature fluctuations induced skew and power consumption of the proposed dual-V DD /dual-frequency clock distribution network are reduced by up to 80% and 76%, respectively, as compared to a standard distribution network operating at the nominal supply voltage with the target system clock frequency.

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A design for digital, dynamic clock deskew

Cited by 25 publications

References 5 publications

Uncertainty in DLL deskewing schemes

Uncertainty in DLL deskewing schemes

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

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