A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware

Song, Shihao; Varshika, M. Lakshmi; Das, Anup; Kandasamy, Nagarajan

doi:10.1109/iccad51958.2021.9643500

Cited by 25 publications

(9 citation statements)

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“…While traditional von Neumann architectures have one or more central processing units physically separated from the main memory, neuromorphic architectures exploit the co-localization of memory and compute, near and in-memory computation [18]. Simultaneously to the tremendous progress in devising novel neuromorphic computing architectures, there has been many recent works that address how to map and compile (trained) SNNs models for efficient execution in neuromorphic hardware [19][20][21][22][23][24][25][26][27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

2022

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A sustainable computing scenario demands more energy-efficient processors. Neuromorphic systems mimic biological functions by employing spiking neural networks for achieving brain-like efficiency, speed, adaptability, and intelligence. Current trends in neuromorphic technologies address the challenges of investigating novel materials, systems, and architectures for enabling high-integration and extreme low-power brain-inspired computing. This review collects the most recent trends in exploiting the physical properties of nonvolatile memory technologies for implementing efficient in-memory and in-device computing with spike-based neuromorphic architectures.

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Section: Introductionmentioning

confidence: 99%

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

2022

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“…In [192], Song et al propose a complete design flow (roughly based on the design flow proposed for embedded multiprocessor systems [193,182,194].) for mapping throughput-constrained SNN applications to a neuromorphic hardware.…”

Section: Application and Hardware Modeling For Predictable Performanc...mentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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Recently, both industry and academia have proposed several different neuromorphic systems to execute machine learning applications that are designed using Spiking Neural Networks (SNNs). With the growing complexity on design and technology fronts, programming such systems to admit and execute a machine learning application is becoming increasingly challenging. Additionally, neuromorphic systems are required to guarantee real-time performance, consume lower energy, and provide tolerance to logic and memory failures. Consequently, there is a clear need for system software frameworks that can implement machine learning applications on current and emerging neuromorphic systems, and simultaneously address performance, energy, and reliability. Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design. We highlight challenges and opportunities that the future holds in the area of system software technology for neuromorphic computing.

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“…PSOPART [27] minimizes spike latency on the shared interconnect, SpiNeMap [9] minimizes interconnect energy, DFSynthesizer [82] maximizes throughput, DecomposedSNN [11] maximizes crossbar utilization, EaNC [90] minimizes overall energy of a machine learning task by targeting both computation and communication energy, TaNC [89] minimizes the average temperature of each crossbar, eSpine [91] maximizes NVM endurance in a crossbar, RENEU [80] minimizes the circuit aging in a crossbar's peripheral circuits, and NCil [86] reduces read disturb issues in a crossbar, improving the inference lifetime. Beside these techniques, there are also other software frameworks [1,3,4,6,12,23,25,38,47,50,54,60,71,75,76,78,85,88] and run-time approaches [10,84], addressing one or more of these optimization objectives.…”

Section: Hardware Implementation Of Machine Learning Inferencementioning

confidence: 99%

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Song¹,

Balaji²,

Das³

et al. 2022

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An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a designtechnology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

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A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware

Cited by 25 publications

References 50 publications

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

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