A design approach dedicated to network-based and conflict-free parallel interleavers

Briki, Aroua; Coussy, Philippe; Martin, Éric

doi:10.1145/2206781.2206819

Cited by 7 publications

(21 citation statements)

References 10 publications

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“…The resulting parallel interleaver architecture can thus be significantly optimized by reducing the cost of interconnection network, network controller and memory controller. In order to find optimized conflict-free memory mapping for both Turbo-Codes and LDPC codes, authors of [6] proposed a memory mapping approach inspired from dual-access memory mapping described in [19]. This solution generates architectures with limited network controller cost and that respect a targeted interconnection network defined by the designer.…”

Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

“…Nevertheless, by analyzing the results, the total area could be strongly optimized by reducing the memory controller area which is the most costly part of such architectures (compared to network cost, see [26]). Figure 4 shows a conflict-free memory mapping obtained for the example presented in figure 2 by applying [6] with a Butterfly Network [28] as design constraint. This memory mapping allows to control the interconnection network complexity and consequently to reduce the cost of the network controller.…”

Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

“…Figure 4. Conflict free memory mapping using [6] Hence, for our example it results in a memory controller that is composed of four dedicated control ROMs. Each ROM contains the control bits and address sequences for the memory bank it is associated to and each command word is randomly stored.…”

Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

“…In addition, memory resources are needed in the controller [6][13] [16] to store the memory mapping (i.e. control words to address memory banks and to drive interconnection networks).…”

Section: Introductionmentioning

confidence: 99%

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A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

Briki¹,

Coussy²

2013

SiPS 2013 Proceedings

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Recent communication standards and storage systems (e.g. wireless access, digital video broadcasting or magnetic storage in hard disk drives) uses error correcting codes such as LDPC (Low Density Parity Check) or Turbo-codes to reliably transfer data between source and destination. For high data rate applications, Turbo and LDPC codes are decoded on parallel architectures. However, parallel architectures suffer from memory access conflicts and efficient memory mapping algorithms are required to design parallel interleaver architectures which are one of the most critical parts of parallel decoders. In this paper, we present a method that finds a conflict-free memory mapping for any interleaving law and associated parallelism constraint. The proposed approach always complies with the interconnection network topology the designer wants to infer. Moreover, contrary to traditional methods, the resulting architecture is optimized by reducing the cost of network and controller (network and memory controller) architectures. Our approach is compared with state of the art techniques and its interest is shown through the design of parallel interleavers used in different industrial applications such as High Speed Downlink Packet Access (HSDPA), Multi BandOrthogonal Frequency-Division Multiplexing Ultra-WideBand (MB-OFDM UWB) and a WiMAX application.

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Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

“…In addition, memory resources are needed in the controller [6][13] [16] to store the memory mapping (i.e. control words to address memory banks and to drive interconnection networks).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

Briki¹,

Coussy²

2013

SiPS 2013 Proceedings

Self Cite

View full text Add to dashboard Cite

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“…control words to address memory banks and to drive interconnection networks). Unfortunately, cost of the controller is not considered for optimization [5].…”

Section: Figure 1 Architecture Overviewmentioning

confidence: 99%

A memory mapping approach for network and controller optimization in parallel interleaver architectures

Briki

Coussy

2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

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Recent communication standards and storage systems uses parallel architectures for error correcting codes (LDPC or Turbocodes) to reliably transfer data between two equipments. However, parallel architectures suffer from memory access conflicts. In this paper, we present a method that finds a conflictfree memory mapping for any interleaving law and any parallelism. The proposed approach always complies with the interconnection network topology the designer wants to infer. Moreover, the resulting architecture is optimized by reducing the cost of network and controller (network and memory controller) architectures.

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Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

Wang

Shen

Sun

et al. 2014

IEEE Trans. Circuits Syst. I

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Abstract-To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multistandard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2 . When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTEAdvanced mode, exceeding the peak data rate requirements for both standards.

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A design approach dedicated to network-based and conflict-free parallel interleavers

Cited by 7 publications

References 10 publications

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

A memory mapping approach for network and controller optimization in parallel interleaver architectures

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

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