A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

Lim, Jeong-Ok; Bae, Jun-Hyun; Jang, Jaeshin; Jung, Hae-Kang; Lee, Hyunbae; Kim, Yongju; Kim, Byungsub; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/tcsii.2015.2468911

Cited by 23 publications

(10 citation statements)

References 5 publications

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“…But it works only at 500MHz signal. In [13], DLL is proposed along with DCC using feedback edge combiner. Here the main focus is on architectures used on SDRAMs that has DLL included to increase the data rate of the channel.…”

Section: Related Workmentioning

confidence: 99%

Duty Cycle Corrector Using Pulse Width Modulation

Patil¹,

Bailey²,

Anuvanahally³

2019

VLSICS

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In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/-1.5% accuracy. The design is simple and the power consumption is 1.01mW.

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Section: Related Workmentioning

confidence: 99%

Duty Cycle Corrector Using Pulse Width Modulation

Patil¹,

Bailey²,

Anuvanahally³

2019

VLSICS

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“…As the memory bandwidth required for mobile devices and computing systems for big data processing such as cloud computing and artificial intelligence (AI) increases, the operating frequency of the memory I/O link is continuously increasing. Recent high-speed DRAMS [1,2,5,6,7,8,9,10] and memory controllers [3,4] operating above multi-Gbps demand very precise 50% on-chip duty-cycle clocks to improve timing margins. However, the clock duty-cycle of a memory system is distorted by impedance mismatches, dispersion and crosstalk noise that occur in memory interface channels operating above multiple GHz.…”

Section: Introductionmentioning

confidence: 99%

“…To eliminate the clock duty-cycle errors in memory interface channels, input clock buffers, and on-chip clock trees, typical high-speed DRAM and memory controllers utilize analog-type, digital-type or hybrid-type duty-cycle corrector (DCC) circuits [1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS).…”

Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

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This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

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“…In order to achieve a memory bus data rate of over 400 Mbps/pin, DDR-x SDRAMs must incorporate an on-chip delay-locked loop (DLL) [1,2,3,4,5,6,7,8,9,10,11,12] that can eliminate skew problems and achieve higher timing margin at high frequencies. To design a DLL that can support both DDR3 and DDR4 specifications at the same time [13,14], the DLL should be locked within 512 clock cycles and operate over a frequency range from 300 MHz to 1.6 GHz using an internal supply voltage of less than 1.2 V. Also, the DLL must be capable of correcting the duty cycle of the distorted input clock so that the data-valid window (tDV) could be widened [2].…”

Section: Introductionmentioning

confidence: 99%

“…Currently, most DDR3/DDR4 SDRAMs use a digital DLL [1,2,3,4,10,11]. One of the reasons for using digital architectures is because DDR3/DDR4 SDRAMs require fast recovery times for various power mode transitions.…”

Section: Introductionmentioning

confidence: 99%

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Yoon

Heo

Kim

2017

IEICE Electron. Express

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A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noisetolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02 mm 2 . The DLL operates over a frequency range of 0.3-2.0 GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48 mW from a 1.1 V supply at 1 GHz.

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A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

Cited by 23 publications

References 5 publications

Duty Cycle Corrector Using Pulse Width Modulation

Duty Cycle Corrector Using Pulse Width Modulation

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

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