A defect tolerant self-organizing nanoscale SIMD architecture

Abstract

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing to the exponentially increasing cost of top-down lithography. Bottom-up manufacturing techniques, like self-assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. Therefore, regardless of fabrication methodology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities. This paper explores a defect tolerant SIMD architecture. A key feature of our design is the ability of a large number of limited capability nodes with high defect rates (up to 30%) to self-organize into a set of SIMD processing elements. Despite node simplicity and high defect rates, we show that by supporting the familiar data parallel programming model the architecture can execute a variety of programs. The architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. On a medium sized system (~1cm 2 area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). For larger systems (>1cm 2 ), the proposed architecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores.

Routing in self-organizing nano-scale irregular networks

“…SOSA [Patwardhan et al 2006c] is a defect-tolerant self-organizing nano-scale SIMD architecture built from a random network of simple computational nodes. SOSA relies on a novel DNA self-assembly process to create small-scale nodes with limited digital compute and storage capabilities.…”

“…Figure 3 compares the average latency of PSIs with all instructions among six test programs simulated by a timing-accurate SOSA simulator. The SOSA simulator is an event-driven simulator where each activity in a node is an event and its latency is a multiple of "time quantum" defined as the time taken to perform one part of the internode asynchronous communication handshake [Patwardhan et al 2006c]. The test programs include Add, a software-emulated floating point program for addition and normalization, BinPack, a pipelined version of integer bin-packing with a first-fit heuristic using N PEs for N bins, GauFilter, GenFilter, and MedFilter which are image processing programs that apply a generic 3x3 filter, a separable Gaussian filter, and a median filter to an NxN image using N 2 PEs, respectively, and finally Search, a program that finds a 32-bit input string in a database using O(N ) PEs for N strings.…”

“…SOSA already ensures deadlock-free routing by using Euler path forwarding and providing three virtual channels [Patwardhan et al 2006c]. Our routing algorithm does not change the routing along VC0 or VC1, but only affects VC2.…”

“…Our analysis is performed primarily in the context of SOSA [Patwardhan et al 2006c], a self-organizing nano-scale SIMD architecture, but is broadly applicable to any system that maps logical rings onto irregular networks. SOSA uses a one-time configuration process to organize the nano-scale irregular physical network into a regular physical network (a tree) by disabling certain links, and then maps a regular logical network (a ring) onto the regular physical network.…”

“…For the networks we examine, there is little difference in the head/tail shortest path on the irregular physical network (a graph) versus the regular physical network (a tree). Therefore, our routing optimizations augment existing Euler path routing techniques [Patwardhan et al 2006c] for trees. In essence, our approach provides express channels between pairs of nodes on an Euler path.…”