A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme

Abstract

This paper presents a high performance sparse matrix-vector multiplication (SpMV) accelerator on the field-programming gate array (FPGA). By exploiting a hardware-friendly storage scheme, named as Variable-Bit-Width Coordinate Block Quasi Compressed Sparse Row, the redundant computation and memory accesses can be reduced greatly through the nested block compression and variable-bit-width column-index encoding schemes. Based on the proposed compression scheme, a deeply-pipelined SpMV accelerator is implemented on a Xilinx Virtex XC7VX485T FPGA platform, which can handle sparse matrices with arbitrary size and sparsity pattern. Experimental results show that the proposed design can gain higher performance for most of the tested matrices and improve the utilization of the memory bandwidth up to 13×, compared with the previous works on the Convey platforms (HC-1 and HC-2ex) and Nvidia Tesla S1070 GPU platform.

Complete three‐phase detection framework for identifying abnormal cervical cells

“…The source codes of this framework will be publicly released on GitHub for the further improvement the performance of this detection problem https://github.com/ylzhhn/ cervical_smear_3phases_detect_sys. In the future, the framework can also be accelerated by the parallel programming techniques [33,34]. Moreover, the analysis to recognise different types of the pre-cancerous cells is a meaningful research question in this field.…”

Hardware accelerator for high accuracy sign language recognition with residual network based on FPGAs

“…Notably, the ResNet network introduced the concept of residual blocks, enabling the training of deeper neural networks, which helps mitigate the vanishing gradient problem [14]. Work on FPGAs, which offer the advantages of low latency, low power consumption, and high flexibility over traditional hardware acceleration solutions, has been widely carried out [15][16][17][18][19][20][21][22][23][24][25][26][27]. However, they face limitations in on-chip resources, and modifications in network architecture necessitate hardware circuit redesign.…”