A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders

Sanchez, O.; Jézéquel, Michel; Rehman, Saeed Ur; Sani, Awais; Coussy, Philippe; Jégo, Christophe

doi:10.1109/sips.2012.18

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…Since the area for the memory banks is the same for each test case, it is not taken into account in these results. This simplification is fair since from [24] it can be observed that these extrinsic memories represent about 10% of the total area (also 10% of total area for PEs, 1% for the interconnection network and the rest -79%-for the control unit). Fig.…”

Section: Experiments and Resultsmentioning

confidence: 99%

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

Reehman

Coussy

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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Parallel hardware architectures are needed to achieve high throughput systems. Unfortunately, efficient parallel architectures require removing memory access conflicts. This is particularly true when designing turbo-codes, channel interleaver or LDPC (Low Density Parity Check) codes architectures which are one of the most critical parts of parallel decoders. Many solutions are proposed in state of the art to find conflict free memory mapping but they are either limited to a subset of constraints, or result in high architectural cost. These drawbacks come from the interleaving law and the incompatibility between this law and the targeted interconnection network (in coder/encoder architecture). In this paper we propose a conflict free memory mapping approach that is able to generate optimized hardware architectures by limiting these drawbacks. The proposed solution constructs a customized interconnection network by analyzing data access patterns defined in the interleaving law. Our approach is then compared to state of the art methods and its interest is shown through the design of parallel interleavers for HSPA.

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Section: Experiments and Resultsmentioning

confidence: 99%

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

Reehman

Coussy

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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“…This is made possible by adding registers in the architectures to deal with conflicting data and memory locations when there is no other solution. Nevertheless, by analyzing the results, the total area could be strongly optimized by reducing the memory controller area which is the most costly part of such architectures (compared to network cost, see [26]). Figure 4 shows a conflict-free memory mapping obtained for the example presented in figure 2 by applying [6] with a Butterfly Network [28] as design constraint.…”

Section: Existing Memory Mapping Approachesmentioning

confidence: 99%

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

Briki¹,

Coussy²

2013

SiPS 2013 Proceedings

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Recent communication standards and storage systems (e.g. wireless access, digital video broadcasting or magnetic storage in hard disk drives) uses error correcting codes such as LDPC (Low Density Parity Check) or Turbo-codes to reliably transfer data between source and destination. For high data rate applications, Turbo and LDPC codes are decoded on parallel architectures. However, parallel architectures suffer from memory access conflicts and efficient memory mapping algorithms are required to design parallel interleaver architectures which are one of the most critical parts of parallel decoders. In this paper, we present a method that finds a conflict-free memory mapping for any interleaving law and associated parallelism constraint. The proposed approach always complies with the interconnection network topology the designer wants to infer. Moreover, contrary to traditional methods, the resulting architecture is optimized by reducing the cost of network and controller (network and memory controller) architectures. Our approach is compared with state of the art techniques and its interest is shown through the design of parallel interleavers used in different industrial applications such as High Speed Downlink Packet Access (HSDPA), Multi BandOrthogonal Frequency-Division Multiplexing Ultra-WideBand (MB-OFDM UWB) and a WiMAX application.

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A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders

Cited by 2 publications

References 16 publications

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

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