A Decomposition Chart Technique to Aid in Realizations with Multiplexers

Langdon,

doi:10.1109/tc.1978.1675048

Cited by 13 publications

(9 citation statements)

References 2 publications

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“…Many synthesis algorithms for different kinds of multiplexer circuits have been developed [117][118][119][120][121][122][123][124][125][126][127][128]. One synthesis method with multiplexers is to find a single multiplexer, if possible of the minimum size, which realizes the given Boolean function [121][122][123]127].…”

Section: Chapter VII Hierarchical Multiplexer Synthesis For Boolean Fmentioning

confidence: 99%

“…One synthesis method with multiplexers is to find a single multiplexer, if possible of the minimum size, which realizes the given Boolean function [121][122][123]127]. Algorithms have been presented in [117,125,128] to find a possible cascade multiplexer circuit of a Boolean function.…”

Section: Chapter VII Hierarchical Multiplexer Synthesis For Boolean Fmentioning

confidence: 99%

“…Algorithms have been presented in [117,125,128] to find a possible cascade multiplexer circuit of a Boolean function. The algorithms [122][123][124][125] are based on graphical methods which allow only the synthesis for functions with up to six variables. A third realization, which will be further developed in this Chapter, is known as multiplexer tree circuit [64,65,[118][119][120]123,124,129].…”

Section: Chapter VII Hierarchical Multiplexer Synthesis For Boolean Fmentioning

confidence: 99%

“…This approach will be adopted here. A similar principle is used for the realization of Boolean functions as cascade multiplexer circuits or single multiplexer circuits, where only one next level module is allowed or no module at all [117,[121][122][123]125,127,128]. In the case that in a particular level of the multiplexer circuit different combinations of k data-select variables require the same number of next level multiplexer modules, a selection should take into account the possible further minimization in the next lower levels of the multiplexer circuit.…”

Section: Vii2 Redundancy Of Multiplexer Modulesmentioning

confidence: 99%

“…It has been shown [63,115,116] that multiplexers are universal logic modules, where a multiplexer of k data-select inputs can realize any function of k + 1 input variables, under the assumption, that the complements of the input variables are also available. Thus, they can be used for the synthesis of multilevel logic networks.One can observe, that an n-variable linear function can be realized by a cascade multiplexer circuit of M(k) multiplexers where [ /I ; 1~multiplexers are necessary.Many synthesis algorithms for different kinds of multiplexer circuits have been developed [117][118][119][120][121][122][123][124][125][126][127][128]. One synthesis method with multiplexers is to find a single multiplexer, if possible of the minimum size, which realizes the given Boolean function [121][122][123]127].…”

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Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Schäfer¹

2000

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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophi~ticated logic design tools. In 2 the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACT™ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates.The mapping to th~new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm".To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended 3 theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks:(1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they can not take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis.To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the sp...

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Section: Chapter VII Hierarchical Multiplexer Synthesis For Boolean Fmentioning

confidence: 99%

Section: Chapter VII Hierarchical Multiplexer Synthesis For Boolean Fmentioning

confidence: 99%

Section: Chapter VII Hierarchical Multiplexer Synthesis For Boolean Fmentioning

confidence: 99%

Section: Vii2 Redundancy Of Multiplexer Modulesmentioning

confidence: 99%

mentioning

confidence: 99%

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Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Schäfer¹

2000

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Graphical exhaustive analysis of minimum MUX synthesis of switching functions

Lotfi¹,

Tosser²

1980

Computers & Electrical Engineering

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Automated synthesis of digital multiplexer networks

Almaini

Miller

1992

IEE Proc. E Comput. Digit. Tech. UK

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A programmed algorithm is presented for the synthesis and optimisation of networks implemented with multiplexer universal logic modules. The algorithm attempts level by level optimisation selecting the control variables that result in minimum number of continuing branches. Cascaded networks, if realisable, are always found and given preference over tree networks, though mixtures of cascade and tree configurations are permitted. The algorithm is programmed in Fortran and tested for single and double control variable modules. In theory, the program can be used for any number of variables for completely and incompletely specified functions.

show abstract

A Decomposition Chart Technique to Aid in Realizations with Multiplexers

Cited by 13 publications

References 2 publications

Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Graphical exhaustive analysis of minimum MUX synthesis of switching functions

Automated synthesis of digital multiplexer networks

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