A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single &lt;italic&gt;LC&lt;/italic&gt; VCO in 90 nm CMOS

Yoon, Jong-Hyeok; Kwon, Seong-Geun; Bae, Hyeon‐Min

doi:10.1109/jssc.2016.2646803

Cited by 14 publications

(4 citation statements)

References 17 publications

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“…In various systems, including satellite communication, RF circuits, and optical communication, a frequency divider plays a vital role. It finds applications in a wide range of scenarios, including phase-locked loops (PLLs) [1,2,3,4], clock and clock recovery circuits [5,6,7], as well as orthogonal signal generation [8,9,10].With the continuous increase in data rates and system performance, there is an increasing need to develop frequency dividers capable of operating in higher frequency. So far, numerous dividers based on different topologies and processes have been reported.…”

Section: Introductionmentioning

confidence: 99%

A broadband ECL static frequency divider in InP DHBT using differential ft-doubler

Xu,

Lou,

et al. 2024

IEICE Electron. Express

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This letter presents a broadband ECL static divider using a 0.8-μ m InP DHBT process. The differential implementation of 𝑓 𝑡 doubler has been employed to extend the bandwidth at the cost of little increase in power dissipation and chip area. The frequency characteristics of the 𝑓 𝑡 -doubler circuit were analyzed. The chip area was 0.47mm*0.44mm and the total power dissipation was 417 mW from dual power supplies of -3.5 V and -2.5 V. The measurement result shows that the frequency divider can operate from 2 GHz to 66 GHz for sinusoidal input signal. The input reference SOF (self-oscillation frequency) is 59 GHz. the output power locates in 0.41 -10.35 dBm. This divider can operate within a frequency range of 2 GHz to 66 GHz, exhibiting a 0.4-𝑓 𝑡 frequency range.

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Section: Introductionmentioning

confidence: 99%

A broadband ECL static frequency divider in InP DHBT using differential ft-doubler

Xu,

Lou,

et al. 2024

IEICE Electron. Express

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“…Another evolution has opted for an analog-to-digital converter (ADC)-based scheme and a great amount of signal processing in the digital domain, [20][21][22][23][24] which leads to large power consumption and loop latency. Even if some solutions have been proposed in previous studies, [25][26][27][28][29][30][31] they either require complex loop topologies 25,31 and large power consumption [26][27][28] or result in a limited capture range. 29,30 The CDR presented in this work is designed based on an NRZ data stream targeting a wide frequency range, low power consumption, and multiphase clock generation.…”

Section: Introductionmentioning

confidence: 99%

“…Another evolution has opted for an analog‐to‐digital converter (ADC)‐based scheme and a great amount of signal processing in the digital domain, 20–24 which leads to large power consumption and loop latency. Even if some solutions have been proposed in previous studies, 25–31 they either require complex loop topologies 25,31 and large power consumption 26–28 or result in a limited capture range 29,30 …”

Section: Introductionmentioning

confidence: 99%

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

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This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm 2 and attains a bit error rate of less than 10 À12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.bang-bang clock and data recovery (BBCDR), current mismatch, frequency detector (FD), hybrid control circuit (HCC), phase interpolator (PI), ring oscillator (RO), R-2R digital-toanalog converter (DAC), switched-capacitor (SC) array, wide capture range

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“…With the continuous expansions of the applications of wired serial communication, the performance, cost, and scalability of clock and data recoveries (CDRs) as the core component of wireline receivers are getting more attention. Referenceless CDRs have the following advantages over existing CDRs that requires a reference clock: First, the operational data rate being neither fixed nor of a few predefined values, a referenceless CDR can adaptively operates at any data rate within the tuning range of DCO [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]. Therefore, it has a wider range of applications and improves the reusability of IPs.…”

Section: Introductionmentioning

confidence: 99%

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

Park

Huang

et al. 2020

IEICE Electron. Express

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This paper presents an all-digital half-rate referenceless CDR with a single direction frequency acquisition achieved. Thanks to asymmetric binary phase detector (ABPD), compared with existed inverse alexander phase detector (IAPD), we changed the input-output characteristic to enable accumulated phase error point in the same direction when frequency error happens while the output of IAPD has no directivity. Once the frequency of the digital controlled oscillator (DCO) enters the pull-in range of the CDR loop, the phase is automatically locked. To improve jitter tolerance (JTOL) performance further, IAPD logic is enabled, and ABPD is disabled after locking. The prototype was implemented in a 28 nm low power CMOS process with a data rate tracking range of 9-11 Gb/s. The measured JTOL is 0.35 UI at high frequency with PRBS31 input data pattern.

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A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single <italic>LC</italic> VCO in 90 nm CMOS

Cited by 14 publications

References 17 publications

A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler

A broadband ECL static frequency divider in InP DHBT using differential <i>f<sub>t</sub></i>-doubler

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

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