A Data-Driven Verilog-A ReRAM Model

Messaris, Ioannis; Serb, Alexantrou; Stathopoulos, Spyros; Khiat, Ali; Nikolaidis, S.; Prodromakis, Themis

doi:10.1109/tcad.2018.2791468

Cited by 79 publications

(72 citation statements)

References 40 publications

(30 reference statements)

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“…The other drawback is a limitation of the memristive devices in terms of the number of resistance levels that can be achieved for particular memristive devices. The future work will include the implementation of the crossbar with a physically realizable memristor [68], evaluation of the performance of the architecture with different memristive devices, evaluation of the abilities of different memristive devices and adjustment of circuit parameters for particular devices.…”

Section: Discussionmentioning

confidence: 99%

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Krestinskaya

Salama

James

2019

IEEE Trans. Circuits Syst. I

121

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The on-chip implementation of learning algorithms would speed-up the training of neural networks in crossbar arrays. The circuit level design and implementation of backpropagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we proposed the analog backpropagation learning circuits for various memristive learning architectures, such as Deep Neural Network (DNN), Binary Neural Network (BNN), Multiple Neural Network (MNN), Hierarchical Temporal Memory (HTM) and Long-Short Term Memory (LSTM). The circuit design and verification is done using TSMC 180nm CMOS process models, and TiO2 based memristor models. The application level validations of the system are done using XOR problem, MNIST character and Yale face image databases.

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Section: Discussionmentioning

confidence: 99%

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Krestinskaya

Salama

James

2019

IEEE Trans. Circuits Syst. I

121

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“…As the memristive technology is not mature [14,15,16], the effect of the real memristive devices on the overall system performance and accuracy should be studied. In addition, the selection of the appropriate memristor material and corresponding non-ideal memristor model for the simulations is also important [17,18].…”

Section: Discussionmentioning

confidence: 99%

Approximate Probabilistic Neural Networks with Gated Threshold Logic

Krestinskaya

James

2018

2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)

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Probabilistic Neural Network (PNN) is a feed-forward artificial neural network developed for solving classification problems. This paper proposes a hardware implementation of an approximated PNN (APNN) algorithm in which the conventional exponential function of the PNN is replaced with gated threshold logic. The weights of the PNN are approximated using a memristive crossbar architecture. In particular, the proposed algorithm performs normalization of the training weights, and quantization into 16 levels which significantly reduces the complexity of the circuit.

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“…We can define switching as a change in resistive state (RS), measured under a fixed read-out voltage, before and after the application of a stimulus of a specific combination of amplitude and pulse width [16]. In an ideal voltage controlled memristive system as described in [17], if any other factors are ignored, the degree of switching should in principle only depend on initial RS (R) and applied stimulus waveform (in this case, voltage amplitude of square wave stimulation V ). However a number of uncertainty factors mean that change in resistance, ∆R, will typically differ for each trial.…”

Section: Methodsmentioning

confidence: 99%

A Memristive Switching Uncertainty Model

Stathopoulos

Serb

Khiat

et al. 2019

IEEE Trans. Electron Devices

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In this paper we endeavour to evaluate and model switching noise in resistive random access memory devices (RRAM). Although noise is always present in physical systems, the sources of which can be attributed to many different effects, in this study we are focusing our attention on a specific typeswitching noise. Using alternating pulse programming and read trains across different voltages we acquire a large dataset below and above the switching threshold and construct what we define as increment plots, ∆R vs. R. Then, through a detailed statistical analysis, we quantify the localised uncertainty among consecutive points using a sliding window of up to N points accounting for any statistical artefacts that arise. By separating the data accumulated from programming and read-out and analysing them individually we can subtract a baseline noise floor from the overall switching uncertainty. In this way we effectively decouple it from other noise sources that affect the device at rest. In the end an F (R, V ) surface can be extracted that closely follows the behaviour of uncertainty of the device during programming. This modelled surface can be used as an approximation of the noise behaviour of the device or it can be readily incorporated as an additional component to existing switching models.

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A Data-Driven Verilog-A ReRAM Model

Abstract: Abstract-

Cited by 79 publications

References 40 publications

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Approximate Probabilistic Neural Networks with Gated Threshold Logic

A Memristive Switching Uncertainty Model

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