A Current-Mode Delay-Based Hysteretic Buck Regulator With Enhanced Efficiency at Ultra-Light Loads for Low-Power Microcontrollers

Ahmed, Muhammad Swilam; Fayed, Ayman

doi:10.1109/tpel.2019.2913151

Cited by 14 publications

(2 citation statements)

References 19 publications

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“…For the regulation of AV DD , we are not using the conventional OPDC scheme which requires fast comparators, as the fast comparator increases the controller's power loss and design difficulty, and degrades the regulation robustness as the switching noise would easily affect the comparator operation [14]. Reference [23] explores a currentmode delay based hysteretic control scheme to regulate the single-output DC-DC buck converter, proving the advantages in quiescent current and design complexity by using a slow comparator for regulation. We propose a slow comparator based OPDC (SC-OPDC) scheme with a synchronous circuit.…”

Section: The Proposed Hybrid Sibto Converter Withmentioning

confidence: 99%

A Hybrid Single-Inductor Bipolar Triple-Output DC–DC Converter With High-Quality Positive Outputs for AMOLED Displays

Mao

Lü

Maloberti

et al. 2023

IEEE Trans. Circuits Syst. I

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This paper presents a hybrid single-inductor bipolar triple-output (SIBTO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays. Generating the bipolar rails V OP and V ON for the pixel array and the analog rail AV DD for the source driver with a single inductor greatly reduces the system size and cost. This work adopts the floating negative output topology for an ultra-clean positive output. In addition, we propose a push-pull charge balancer to compensate and regulate the V OP , improving the line and load regulation with continuous currents and acceptable power consumption. This work also proposed a slow-comparator based ordered power distributive control (SC-OPDC) to regulate the AV DD with a pulse-skipping scheme to reduce the power loss. The designed power transistor buffers with adaptive deadtime control improve power conversion efficiency and decrease the required minimum load current of AV DD . The proposed SIBTO converter, implemented in 0.18-µm BCD process, operates at 1.67 MHz. It achieves a peak efficiency of 94.1% at 0.88 W output and a maximum output power of 3.67 W with an efficiency of 87%. The maximum output voltage ripples are 5 mV, 17 mV, and 7.5 mV for V OP , V ON , and AV DD , respectively.

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Section: The Proposed Hybrid Sibto Converter Withmentioning

confidence: 99%

A Hybrid Single-Inductor Bipolar Triple-Output DC–DC Converter With High-Quality Positive Outputs for AMOLED Displays

Mao

Lü

Maloberti

et al. 2023

IEEE Trans. Circuits Syst. I

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“…In Figure 12a, as the switching frequency increases, the coil-wire length, l, and skin depth, δ, both decrease. Based on calculations, since the effect of coil-wire length reduction According to Figures 11b and 12b, the efficiency boundaries of PSiPs are predicted and verified in Figure 13 [42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61]. In order to eliminate the effect of input and output voltages on efficiency, the efficiencies in the literature are normalized according to the following:…”

mentioning

confidence: 99%

Technical Reviews of Power Loss Optimization in High-Frequency PSiPs—In Relation to Power Switches and Power Inductors

Wang,

Zhang,

et al. 2023

Applied Sciences

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Power losses of switches and inductors are consistent challenges that hinder the development of high-frequency power supply in package (PSiP). This paper investigates the roadmap for power loss optimizations of switches and inductors in high-frequency PSiPs. Firstly, a size and parallel quantity design method to reduce power loss in an integrated Si LDMOSFET is provided with comprehensive consideration of switching frequency and power levels. Secondly, quality factors of different air-core inductors are analyzed with consideration of geometric parameters and skin effect, which provides the winding structure optimization to reduce power losses. The power losses of the integrated Si LDMOSFET and air-core inductors are both reduced to less than 10% of the output power at 1~100 MHz switching frequency and 0.1~10 W power level. Finally, based on the above optimizations, power losses of switches and inductors are calculated with switching frequency and power level. Combining the calculated results, this paper predicts the efficiency boundaries of PSiPs. Upon efficiency normalization with consideration of input and output voltage levels, all the predictions are consistent with the published literature. The efficiency predication error is 1~15% at 1~100 MHz switching frequency and 0.1~10 W power level. The above power loss optimizations improve the efficiency, which provides potential roadmaps for achieving high-frequency PSiPs.

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High-power buck chip design for vehicle far/near headlights

Hsia

Sung-Keng

2022

Analog Integr Circ Sig Process

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A Current-Mode Delay-Based Hysteretic Buck Regulator With Enhanced Efficiency at Ultra-Light Loads for Low-Power Microcontrollers

Cited by 14 publications

References 19 publications

A Hybrid Single-Inductor Bipolar Triple-Output DC–DC Converter With High-Quality Positive Outputs for AMOLED Displays

A Hybrid Single-Inductor Bipolar Triple-Output DC–DC Converter With High-Quality Positive Outputs for AMOLED Displays

Technical Reviews of Power Loss Optimization in High-Frequency PSiPs—In Relation to Power Switches and Power Inductors

High-power buck chip design for vehicle far/near headlights

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