A current-mode back-end for a sensor microsystem

Ajbl, Andrea; Pastre, Marc; Kayal, Maher

doi:10.1109/newcas.2011.5981271

Cited by 9 publications

(6 citation statements)

References 13 publications

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“…The output signal is demodulated and converted into a current I OUT . A discrete voltage-to-current converter (V-I) [17], shown in Fig. 6, is designed for signal demodulation.…”

Section: ) Signal and Reference Demodulatormentioning

confidence: 99%

A Fully Integrated Hall Sensor Microsystem for Contactless Current Measurement

Ajbl,

Pastre,

Kayal

2013

IEEE Sensors J.

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Contactless current measurement based on Halleffect sensors can be performed in either closed-or open-loop configuration. In this paper an open-loop sensor system with a current-mode output is described. The system measures the magnetic field induced around the current path targeting high linearity, accuracy, and speed. As the accuracy of the Hall sensor microsystem is affected by temperature-dependent offset and sensitivity of the sensing element, system-level solutions are developed to minimize these effects. The full system integration represents a design challenge as both voltage and current references are directly involved in the sensitivity calibration and both contribute to the system sensitivity drift. The measurements show a sensitivity drift lower than 80 ppm/°C, the offset drifts less than 300 nT/°C and the nonlinearity is less than ±0.08%. The effects of the varying external field on the calibration loop are analyzed and the theoretical prediction is validated by measurement.Index Terms-Current output, full integration, Hall-effect sensor, sensitivity calibration.

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“…The output signal is demodulated and converted into a current I OUT . A discrete voltage-to-current converter (V-I) [17], shown in Fig. 6, is designed for signal demodulation.…”

Section: ) Signal and Reference Demodulatormentioning

confidence: 99%

A Fully Integrated Hall Sensor Microsystem for Contactless Current Measurement

Ajbl,

Pastre,

Kayal

2013

IEEE Sensors J.

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“…Ajbl et. al [20] had presented an integrated Hall-sensor micro-system for readout of magnetic fields. The system is capable of resolving Hall-sensor voltages upto 400 nV.…”

Section: B Experiments With Cross-bar Hall Sensormentioning

confidence: 99%

A 126 μW Readout Circuit in 65 nm CMOS With Successive Approximation-Based Thresholding for Domain Wall Magnet-Based Random Number Generator

et al. 2020

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We present a novel readout circuit for a ferromagnetic Hall cross-bar based random number generator. The random orientation of magnetic domains are result of anomalous Hall-effect. These ferromagnetic Hall cross-bar structures can be integrated with the read out circuit to form a plug and play random number generator. The system can resolve up to 15-20 µV Hall-voltages from Hall probe. Application of current densities around 10 12 A/m 2 through the Ferromagnetic Hall cross-bar produces random Hall-voltage on the output terminals. To amplify the weak Hall-voltages (10-100 µV) in the presence of DC offsets, a modulation scheme is used to up-convert the signal and a band-pass amplifier is used to amplify the modulated signal. The band-pass amplifier circuit, motivated by neural recording amplifier is designed in 65nm CMOS and consumes 126 µW of power from a 1.2 V supply. Further, we present a successive approximation algorithm and its embedded implementation to set the desired threshold for digitizing the amplified Hall-voltage in presence of signal drift. Experimental results show that the resulting system can tolerate drifts in voltage up to 440 µV. I. INTRODUCTIONRandom bit streams find application in generating keys in cryptography and initialization of parameters in a encrypted communication protocols. Random number generators are useful in realising Physically Unclonable Function (PUF) in microprocessors [1], [2]. These streams are also useful in stochastic simulations, gaming and events where random sampling is required. Random number generators can be divided into two classes based on their source, namely true random number generator (TRNG) and pseudo random number generator (PRNG). TRNG generates randomness from inherent stochastic physical feature of the source. On the other hand PRNG generates lengthy stream of digital bits which are difficult to predict. Most on-chip TRNG of present day use techniques like sampling of thermal noise [3] or exploiting meta stability of latching circuits [4]. Recently, magnetic random number generators (MRNG) have been proposed which *Corresponding Author is Arindam Basu. Equal contribution of Govind and Joydeep.

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“…A folded cascode amplifier with gain boosting [33] is adopted to improve the loop gain of the feedback, as shown in Fig. 11.…”

Section: B Sc C2v With Reference Capacitormentioning

confidence: 99%

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

Wang

Dehollain

2015

IEEE Sensors J.

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This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to-voltage (C2V) converter combined with an analog-to-digital converter (ADC), are optimized at system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of a single-stage C2V is provided to prevent cascade amplification. The gain-boosting technique is utilized in the operational transconductance amplifier design to improve the closed-loop linearity. The correlated double sampling technique attenuates the dc offset and low-frequency flicker noise from C2V. A 10-b successive approximation register ADC digitizes the output of C2V. The total area of the digital-to-analog (DAC) array is limited not only by the matching behavior, but also by the noise performance of C2V. The rail-to-rail ability is required to render the compatibility with various possible sensor inputs. A single-ended cascaded binary-weighted capacitive DAC is used to implement the charge redistribution binary search algorithm. The circuit is implemented in a 0.18-µm CMOS technology and occupies an area of 1.2 mm 2 . The tested prototype shows 0.69% nonlinearity in mode 1 and 1.38% nonlinearity in mode 2. The SNR of mode 1 is 50.1 dB and that of mode 2 is 36.5 dB, which meets the specification of 7.32 b in mode 1 and 5.32 b in mode 2. The total power consumption of the capacitive sensor interface is 70 µW.Index Terms-Capacitive sensor interface, C2V, SAR ADC, CDS, opamp, noise optimization, power-efficient system.

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A current-mode back-end for a sensor microsystem

Cited by 9 publications

References 13 publications

A Fully Integrated Hall Sensor Microsystem for Contactless Current Measurement

A Fully Integrated Hall Sensor Microsystem for Contactless Current Measurement

A 126 μW Readout Circuit in 65 nm CMOS With Successive Approximation-Based Thresholding for Domain Wall Magnet-Based Random Number Generator

Design and Implementation of a 46-kS/s CMOS SC Dual-Mode Capacitive Sensor Interface With 50-dB SNR and 0.7% Nonlinearity

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