A Current Attenuator for Efficient Memristive Crossbars Read-Out

Mohan, Charanraj; Rosa, José M. de la; Vianello, Elisa; Perniola, L.; Reita, C.; Linares-Barranco, B.; Serrano-Gotarredona, Teresa

doi:10.1109/iscas.2019.8702604

Cited by 3 publications

(1 citation statement)

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“…In order to make it possible to implement the postsynaptic drivers on-chip, one solution is to downscale the memristor currents by several orders of magnitude before integrating them. This can be done by using multi-decade current down-scaling circuits, which we have investigated before [86]. In that case, offset voltage calibration should be applied both at the pre-synaptic lines and at the post-synaptic lines of the memristor crossbar.…”

Section: Conclusion and Future Outlookmentioning

confidence: 99%

Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration

et al. 2021

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Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One drawback of OxRAM based neuromorphic systems is the relatively low ON resistance of OxRAM synapses (in the range of just a few kilo-ohms). This requires relatively large currents (many micro amperes per synapse), and therefore imposes strong driving capability demands on peripheral circuitry, limiting scalability and low power operation. After learning, however, a read inference can be made low-power by applying very small amplitude read pulses, which require much smaller driving currents per synapse. Here we propose and experimentally demonstrate a technique to reduce the amplitude of read inference pulses in monolithic neuromorphic CMOS OxRAM-synaptic crossbar systems. Unfortunately, applying tiny read pulses is non-trivial due to the presence of random DC offset voltages. To overcome this, we propose finely calibrating DC offset voltages using a bulk-based three-stage on-chip calibration technique. In this work, we demonstrate spiking pattern recognition using STDP learning on a small 4x4 proof-of-concept memristive crossbar, where on-chip offset calibration is implemented and inference pulse amplitude could be made as small as 2mV. A chip with pre-synaptic calibrated input neuron drivers and a 4x4 1T1R synapse crossbar was designed and fabricated in the CEA-LETI MAD200 technology, which uses monolithic integration of OxRAMs above ST130nm CMOS. Custom-made PCBs hosting the postsynaptic circuits and control FPGAs were used to test the chip in different experiments, including synapse characterization, template matching, and pattern recognition using STDP learning, and to demonstrate the use of on-chip offset-calibrated low-power amplifiers. According to our experiments, the minimum possible inference pulse amplitude is limited by offset voltage drifts and noise. We conclude the paper with some suggestions for future work in this direction.

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Section: Conclusion and Future Outlookmentioning

confidence: 99%