A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

Ruffino, Andrea; Yang, Tsung-Yeh; Michniewicz, John; Peng, Yang; Charbon, Edoardo; González-Zalba, M. Fernando

doi:10.1038/s41928-021-00687-6

Cited by 45 publications

(25 citation statements)

References 49 publications

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“…Fabricating the qubits and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds in error-correction protocols, and offer potential solutions to wiring and layout challenges [7,[77][78][79][80][81]. Integrating classical and quantum devices monolithically, using CMOS processes, enables the quantum processor to profit from the most mature industrial technology for the fabrication of large-scale circuits [35]. We show that this architecture allows for compilation strategies which inherit the favourable square-root scaling of compilation overhead in 2d structure and outperform the best in class compilation strategy of 1d chains, not only asymptotically, but also down to the minimal structure of a single square.…”

Section: Discussionmentioning

confidence: 99%

“…We then investigate compilation strategies for the proposed 2d architecture and demonstrate a square-root scaling of the compilation overhead, which outperforms the linear overhead of 1d devices, not only asymptotically, but also down to its smallest building block which is likely to be investigated first in future experiments. This allows for balancing the trade-off between compilation overhead and creating space in between the qubit modules which can be beneficial for colocation of classical control and readout electronics [10,34,35] and alleviating contact routing issues [9,24,36,37]. Overall, this proposal should provide a compelling path to scaling, which could be manufactured with industrial CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

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Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Crawford¹,

Cruise²,

Mertig³

et al. 2022

Preprint

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Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardware elements, we propose a modular sparse 2d spin-qubit architecture with unit cells consisting of diagonally-oriented squares with nanowires along the edges and junctions on the corners. We show that this architecture allows for compilation strategies which outperform the bestin-class compilation strategy for 1d chains, not only asymptotically, but also down to the minimal structure of a single square. The proposed architecture exhibits favorable scaling properties which allow for balancing the trade-off between compilation overhead and colocation of classical control electronics within each square by adjusting the length of the nanowires. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes. Finally, we note that our compilation strategies, while being inspired by spin-qubits, are equally valid for any other quantum processor with sparse 2d connectivity.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Crawford¹,

Cruise²,

Mertig³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…1a has enabled important demonstrations over the past 20 years, it will become very cumbersome for few hundred qubits and may even be unachievable for the million of physical qubits that are required for fault tolerant quantum computing [10]. To avoid this wiring bottleneck, integrated cryogenic control platforms are being developed to control a larger number of spin qubits [9][10][11][12][13][14], while limiting the control electronics required at room temperature (See Fig. 1b).…”

Section: Introductionmentioning

confidence: 99%

“…1a and b) using DC signals, typically in the ±1 V range with at least a 100 µV resolution, while maintaining a thermal budget in the order of a milliwatt or below per DC source [9,11]. A first integrated solution based on switched-capacitor circuits and charge-locking, which is conceptually close to dynamic random access memories (DRAMs), has been proposed to perform simultaneous charge carrier confinement for several quantum dots [12,15]. However, this approach requires qubits that have similar electrical behaviour, which has yet to be demonstrated for silicon spin qubits.…”

Section: Introductionmentioning

confidence: 99%

Memristor-based cryogenic programmable DC sources for scalable in-situ quantum-dot control

Pierre-Antoine¹,

Beilliard²,

Graveline³

et al. 2022

Preprint

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Current quantum systems that are based on spin qubits are controlled by classical electronics located outside the cryostat at room temperature. This approach creates a major wiring bottleneck, which is one of the main roadblocks toward truly scalable quantum computers. Thus, we propose a scalable memristor-based programmable DC source that can be used to perform biasing of quantum dots inside the cryostat (i.e., in-situ). This novel cryogenic approach would enable us to control the applied voltage on the electrostatic gates by programming the resistance of the memristors, thus storing in the latter the appropriate conditions to form the quantum dots. In this study, we first demonstrate multilevel resistance programming of TiO2-based memristors at 4.2 K, which is an essential feature to achieve voltage tunability of the memristor-based DC source. We then report hardware-based simulations of the electrical performance of the proposed DC source. A cryogenic TiO2-based memristor model fitted on our experimental data at 4.2 K was used to show a 1 V voltage range and 100 µV in-situ memristor-based DC source. Finally, we simulate the biasing of double quantum dots, enabling sub-2 minutes in-situ charge stability diagrams. This demonstration is a first step towards more advanced cryogenic applications for resistive memories, such as cryogenic control electronics for quantum computers.

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“…This approach is also cheaper to implement experimentally as the qubit can be operated at temperatures up to 1 K and beyond while maintaining state initialization fidelities over 99.9%. Current efforts in scaling up spin qubit architectures [28][29][30] require on-chip control electronics that generate heat. Hence, initialization of spin qubits at higher temperatures [31][32][33][34][35][36], socalled hot qubits, is currently of very high interest.…”

Section: Introductionmentioning

confidence: 99%

State Initialization of a Hot Spin Qubit in a Double Quantum Dot by Measurement-Based Quantum Feedback Control

Aarab¹,

Azouit²,

Reiher³

et al. 2022

Preprint

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A measurement-based quantum feedback protocol is developed for spin state initialization in a gate-defined double quantum dot spin qubit coupled to a superconducting resonator. The protocol improves qubit state initialization as it is able to robustly prepare the spin in shorter time and reach a higher fidelity, which can be pre-set. Being able to pre-set the fidelity aimed at is a highly desired feature enabling qubit initialization to be more deterministic. The protocol developed herein is also effective at high temperatures, which is critical for the current efforts towards scaling up the number of qubits in quantum computers.

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A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

Cited by 45 publications

References 49 publications

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

Memristor-based cryogenic programmable DC sources for scalable in-situ quantum-dot control

State Initialization of a Hot Spin Qubit in a Double Quantum Dot by Measurement-Based Quantum Feedback Control

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