A critical net reshape-router for high-performance VLSI layout design

Abstract

We present a new critical net reshape-router for high-performance VLSI layout design. Our router firstly rips up a critical-net and calculates its approximate RMST (Rectilinear Minimum Steiner Tree) and puts the restricted area for reshape routing. Secondly a multi-layer maze router searches the path of the net inside the restricted area. Our router can search the approximate optimal shape of RMST and save the critical net delay. We evaluated by using several placement data of 8bit MPU. The experimental results show that the critical net length is reduced about 4.4% to 9.5% on average compared to the original net length.