A CPU, GPU, FPGA System for X-Ray Image Processing Using High-Speed Scientific Cameras

Binotto, Alécio Pedro Delazari; Doering, D.; Stetzelberger, Thorsten; McVittie, Patrick; Zimmermann, S.; Pereira, Carlos Eduardo

doi:10.1109/sbac-pad.2013.1

Cited by 10 publications

(3 citation statements)

References 18 publications

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“…It has been understood that to achieve high performance and power efficiency, different kinds of applications have different hardware requirements. Binotto et al [4] used a heterogeneous system of CPU, GPU and FPGA for X-ray image processing using high-speed scientific cameras. Also, Skalicky et al [5] performed a distributed execution of transmural electrophysiological imaging with a heterogeneous system comprised of CPU, GPU and FPGA.…”

Section: Motivation and Problem Statementmentioning

confidence: 99%

“…Also, Skalicky et al [5] performed a distributed execution of transmural electrophysiological imaging with a heterogeneous system comprised of CPU, GPU and FPGA. It is shown in [4], [5] and many other works that using a heterogeneous system can give better performances in terms of total execution time, power efficiency and system utilization as compared to homogeneous systems.…”

Section: Motivation and Problem Statementmentioning

confidence: 99%

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Alternative Processor Within Threshold: Flexible Scheduling on Heterogeneous Systems

López

Karia

2017

2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Computing systems have become increasingly heterogeneous contributing to higher performance and power efficiency. However, this is at the cost of increasing the overall complexity of designing such systems. One key challenge in the design of heterogeneous systems is the efficient scheduling of computational load. To address this challenge, this paper thoroughly analyzes state of the art scheduling policies and proposes a new dynamic scheduling heuristic: Alternative Processor within Threshold (APT). This heuristic uses a flexibility factor to attain efficient usage of the available hardware resources, taking advantage of the degree of heterogeneity of the system. In a GPU-CPU-FPGA system, tested on workloads with and without data dependencies, this approach improved overall execution time by 16% and 18% when compared to the second-best heuristic. 10 Table 16. APT kernel allocation analyses for DFG Type-2 graphs.

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Section: Motivation and Problem Statementmentioning

confidence: 99%

Section: Motivation and Problem Statementmentioning

confidence: 99%

Alternative Processor Within Threshold: Flexible Scheduling on Heterogeneous Systems

López

Karia

2017

2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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“…Thus, in the long run, beneficial accelerators might just show up in every such machine. Given the complementary advantages of different accelerator architectures for many applications [2], this could potentially even lead to multiple different accelerators per machine. First incarnations of such innovative multi-accelerator architectures [55,60] have already been explored.…”

Section: Introductionmentioning

confidence: 99%

Transparent Acceleration for Heterogeneous Platforms With Compilation to OpenCL

Riebler

Vaz

Kenter

et al. 2019

ACM Trans. Archit. Code Optim.

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Multi-accelerator platforms combine CPUs and different accelerator architectures within a single compute node. Such systems are capable of processing parallel workloads very efficiently while being more energy efficient than regular systems consisting of CPUs only. However, the architectures of such systems are diverse, forcing developers to port applications to each accelerator using different programming languages, models, tools, and compilers. Developers not only require domain-specific knowledge but also need to understand the low-level accelerator details, leading to an increase in the design effort and costs.To tackle this challenge, we propose a compilation approach and a practical realization called HTrOP that is completely transparent to the user. HTrOP is able to automatically analyze a sequential CPU application, detect computational hotspots, and generate parallel OpenCL host and kernel code. The potential of HTrOP is demonstrated by offloading hotspots to different OpenCL-enabled resources (currently the CPU, the generalpurpose GPU, and the manycore Intel Xeon Phi) for a broad set of benchmark applications. We present an in-depth evaluation of our approach in terms of performance gains and energy savings, taking into account all static and dynamic overheads. We are able to achieve speedups and energy savings of up to two orders of magnitude, if an application has sufficient computational intensity, when compared to a natively compiled application.This article is an extension of a conference paper/poster at PPoPP'18 [49]. Prior work only outlined the tool flow and the parallelization mechanism. Evaluation is entirely new, including energy measurements and trends over several data points per application.

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