A corner stitching compliant B&lt;sup&gt;&amp;#x2217;&lt;/sup&gt;-tree representation and its applications to analog placement

Tsao, Hui-Fang; Chou, Pang-Yen; Huang, Shih-Lun; Chang, Yao-Wen; Chen, Duan-Ping; Liu, Dick

doi:10.1109/iccad.2011.6105377

Cited by 13 publications

(17 citation statements)

References 19 publications

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“…In this section, we first give a brief review of the CB-tree [14] and then formulate the DPL-aware analog placement problem.…”

Section: Preliminariesmentioning

confidence: 99%

“…To handle the analog placement problem, most previous works apply topological floorplan representations such as sequence-pair [4], TCG-S [7], hierarchical B*-tree (HB*-tree) [8], O-tree [12], and corner stitching compliant B*-tree (CB-tree) [14]. Although various analog design constraints, such as symmetry, proximity, variant, fixed-boundary, minimum-separation, and boundary constraints, have been studied in previous works, DPL is not considered in these previous works.…”

Section: Mask1mentioning

confidence: 99%

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Double patterning lithography-aware analog placement

Chien

Chen³

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Double patterning lithography (DPL) is one of the most promising solutions for the 28nm technology node and beyond. The main idea of DPL is to decompose the layout into two sub-patterns and manufacture the layout by two masks. In addition to traditional analog design constraints, the pre-coloring constraint should also be considered, in which patterns of critical or sensitive modules have predefined masks before layout decomposition to reduce mismatches. In this paper, we present the first work that considers DPL during analog placement and simultaneously minimizes area, wirelength, and DPL conflicts. We first propose an extended conflict graph (ECG) to represent the relation between patterns of analog modules and apply an integer linear programming (ILP) formulation to determine the orientation of each module and the color of each pattern for conflict minimization. ILP reduction schemes are proposed to further reduce the runtime. Finally, we present a three-stage flow and DPL-aware perturbations to obtain desired solutions. Experimental results show that the proposed flow can effectively and efficiently reduce area, wirelength, and DPL conflicts.

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“…In this section, we first give a brief review of the CB-tree [14] and then formulate the DPL-aware analog placement problem.…”

Section: Preliminariesmentioning

confidence: 99%

Section: Mask1mentioning

confidence: 99%

Double patterning lithography-aware analog placement

Chien

Chen³

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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“…Zhang et al [23] combined TCG and SP to shorten the TCG perturbation time. Tsao et al [16] added the corner-stitching data structure during HB*-tree packing such that many other analog placement requirements can be simultaneously considered in addition to the symmetric placements.…”

Section: Introductionmentioning

confidence: 99%

“…Following the symmetric-feasible conditions or symmetryisland formulation, [3], [7], [8], [12], [15], [16], [23] tried to improve runtime and solution quality in terms of layout area by introducing more data structures and different algorithms. Balasa et al [3] imposed segment trees to improve the B*-tree packing time from O(n 2 ) to O(n lg n).…”

Section: Introductionmentioning

confidence: 99%

Augmenting slicing trees for analog placement

Chiang

Chang

et al. 2012

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD

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The slicing-tree representation had been proven to be very effective and efficient in optimizing floorplanning/placement and handling design/layout migration in modern system-on-chips (SoCs). However, none of the previous works introduced any symmetric-feasible condition in the slicing trees for analog device-level placement. This paper augments the slicing trees by introducing a new insertion operation and presents the symmetric-feasible conditions. Based on the augmented slicing trees and the symmetric-feasible conditions, various symmetric placements can be effectively explored during analog placement optimization.

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“…However the complexity comes from analog constraints such as symmetry or proximity. Most reported approaches have focused on area minimization meeting some analog constraints [11,12]. However, an essential aspect in area minimization of a given analog floorplan is the variant selection problem, i.e., the determination of the specific implementation of each block among a set of possible realizations.…”

Section: Introductionmentioning

confidence: 99%