A Conversion of Empirical MOS Transistor Model Extracted From 180 nm Technology To EKV3.0 Model Using MATLAB

Ayed, Amine; Lahiani, Mongi; Ghariani, Hamadi

doi:10.14569/ijacsa.2016.070712

Cited by 1 publication

(1 citation statement)

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“…This first step of data declaration ends with the introduction of some technological parameters of the transistors which were needed to evaluate the jitter, the intrinsic and extrinsic capacitances involved in the calculation of the total load capacitance seen at the output of the delay cell. Now, using the results of the identification algorithm discussed in [7], the EKV parameters of the transistors were declared in a three-dimensional space (V D , V S , L). The sizing space in this program was defined in 2D by means of the log vectors q F1 and q F2 varying on a logarithmic scale.…”

Section: Dimensioning Algorithm Of Vcomentioning

confidence: 99%

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Ayed¹,

Ghariani²

2017

ijacsa

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Abstract-In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz.

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Section: Dimensioning Algorithm Of Vcomentioning

confidence: 99%