A continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface (DDI)

Abstract

This paper presents a continuous-time equalizer adopting a clock attenuation tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock attenuation. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in 0.18-µm CMOS technology. Simulation results summarize that eye-width of minimum 0.75UI is achieved until −33 dB channel loss at 1.65 Gbps. The average power consumption of the equalizer is 3.42 mW per channel, a very low value in comparison to those of previous researches, and the effective area is 0.127 mm 2 . Keywords: continuous-time equalizer, channel loss tracking Classification: Integrated circuits

8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface

“…Our idea is to detect the clock attenuation at a receiver and use the attenuation signal to all four adaptive equalizers: three signal channels and a clock channel. Such equalizer was proposed and the simulation results were reported briefly in [9] which exhibited that we can curtail three adaptive attenuation detectors in a multi-channel DDI, and can eliminate complex and large feed-back loops.…”