A consistency checker for memory subsystem traces

Abstract

Verifying the memory subsystem in a modern shared-memory multiprocessor is a big challenge. Optimized implementations are highly sophisticated, yet must provide subtle consistency and liveness guarantees for the correct execution of concurrent programs. We present a tool that supports efficient specification-based testing of the memory subsystem against a range of formally specified consistency models. Our tool operates directly on the memory subsystem interface, promoting a compositional approach to system-on-chip verification, and can be used to search for simple failure cases-assisting rapid debug. It has recently been incorporated into the development flows of two open-source implementations-Berkeley's Rocket Chip (RISC-V) and Cambridge's BERI (MIPS)-where it has uncovered a number of serious bugs.

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

“…RVFI-DII instruction streams injected with specified timestamps into multiple shared memory cores should allow precise stimulation of concurrency behaviors. These would require a more advanced verification engine that tests RVFI traces not only for equivalence, but also against higher-level memory-model semantics -as in Axe [9].…”