A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors

Nageswaran, Jayram Moorkanikara; Dutt, Nikil; Krichmar, Jeffrey L.; Nicolau, Alex; Veidenbaum, Alexander V.

doi:10.1016/j.neunet.2009.06.028

Cited by 170 publications

(106 citation statements)

References 21 publications

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“…Furthermore, some physical models are fully irregular. For example, a spiking neural network model, which simulates a human brain cortical network, consists of interconnected groups of neurons with statistically generated connectivity [Nageswaran et al 2009]. Such models result in random, commonly nonplanar graph structures that make embedding difficult, if not impossible.…”

Section: Placement Of Nonstructured Physical Modelsmentioning

confidence: 99%

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Miller

Vahid

Givargis

et al. 2014

ACM Trans. Reconfigurable Technol. Syst.

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Physical models utilize mathematical equations to characterize physical systems like airway mechanics, neuron networks, or chemical reactions. Previous work has shown that field programmable gate arrays (FPGAs) execute physical models efficiently. To improve the implementation of physical models on FPGAs, this article leverages graph theoretic techniques to synthesize physical models onto FPGAs. The first phase maps physical model equations onto a structured virtual processing element (PE) graph using graph theoretic folding techniques. The second phase maps the structured virtual PE graph onto physical PE regions on an FPGA using graph embedding theory. A simulated annealing algorithm is introduced that can map any physical model onto an FPGA regardless of the model's underlying topology. We further extend the simulated annealing approach by leveraging existing graph drawing algorithms to generate the initial placement. Compared to previous work on physical model implementation on FPGAs, embedding increases clock frequency by 25% on average (for applicable topologies), whereas simulated annealing increases frequency by 13% on average. The embedding approach typically produces a circuit whose frequency is limited by the FPGA clock instead of routing. Additionally, complex models that could not previously be routed due to complexity were made routable when using placement constraints.

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Section: Placement Of Nonstructured Physical Modelsmentioning

confidence: 99%

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Miller

Vahid

Givargis

et al. 2014

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

“…While not reaching the low power consumption [18] or speed [28] of dedicated analog hardware, due to its archi tecture the SpiNNaker System offers a compromise between performances of neuromorphic chips [17] and programmable, standard computing systems [2], within a low power budget of 1 Watt/SpiNNaker Chip [15]. Moreover it offers a custom packet switch network based on a Multicast Router [26], which is easily reconfigurable and less power consuming than a circuit-switched architecture [24] [5], and a memory system which is local to every chip, circumventing the challenges needed on GPUs to access memory [3] and maintain process coherency [25], while at the same time keeping power con sumption lower than such systems. In this sense the SpiNNaker architecture is ideal for exploratory studies on large scale mod els which require programmability and fast reconfigurability within a tolerable power budget.…”

Section: Spinnaker Systemmentioning

confidence: 99%

Real time on-chip implementation of dynamical systems with spiking neurons

Galluppi

Davies

Furber

et al. 2012

The 2012 International Joint Conference on Neural Networks (IJCNN)

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Abstract-Simulation of large-scale networks of spiking neu rons has become appealing for understanding the computational principles of the nervous system by producing models based on biological evidence. In particular, networks that can assume a variety of (dynamically) stable states have been proposed as the basis for different behavioural and cognitive functions. This work focuses on implementing the Neural EngineeringFramework (NEF), a formal method for mapping attractor net works and control-theoretic algorithms to biologically plausible networks of spiking neurons, on the SpiNNaker system, a massive programmable parallel architecture oriented to the simulation of networks of spiking neurons. We describe how to encode and decode analog values to patterns of neural spikes directly on chip. These methods take advantage of the full programmability of the ARM968 cores constituting the processing base of a SpiNNaker node, and exploit the fast Network-on-chip for spike communication.In this paper we focus on the fundamentals of representing, transforming and implementing dynamics in spiking networks.We show real time simulation results demonstrating the NEF principles and discuss advantages, precision and scalability. More generally, the present approach can be used to state and test hypotheses with large-scale spiking neural network models for a range of different cognitive functions and behaviours.

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“…A remarkable early attempt using a processor with strong similarities to SpiNNaker, the Datawave chip [24], appears not to have been pursued further because of the limited commercial success and eventual disappearance of the hardware. While the increasing ubiquity of standard multicore microprocessors introduces an obvious opportunity to exploit parallelism, other, more creative approaches use field-programmable gate arrays (FPGA's) [45] and graphics processor units (GPU's) [38]. FPGA's, in particular, offer an attractive possibility: reconfigurable computing.…”

Section: Adapted General-purpose Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

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Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

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A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors

Cited by 170 publications

References 21 publications

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Real time on-chip implementation of dynamical systems with spiking neurons

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

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