A Concept of Vector Clock Utilization in an Iterative Tracing Approach for Distributed Embedded Systems

Höttger, Robert; Igel, Burkhard

doi:10.1145/2764967.2764969

Cited by 2 publications

(3 citation statements)

References 5 publications

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“…For tasks i and k with a dependent relation, task k can be in the same or latter layer as task i as described in (12). g ilk is calculated using the inequality (13), which implies that if both s i,l and l0≥l s k,l0 are 1, then it is 1; otherwise, it is 0. However, if two tasks are assigned to different SPEs, task k can exist only in the layers after task i as described in (14).…”

Section: A Formulation Of One-step Ilpmentioning

confidence: 99%

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Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Wu,

Kumano,

Marume

et al. 2024

IEEE Access

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In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model. Solving data-and task-parallelism is crucial during this process. For data parallelism, a RISC-V Simulink library written in vector codes was prepared for blocks with sufficient vector or matrix calculations. Moreover, large inputs can be divided, which means that tasks can be executed simultaneously using multiple cores. For task parallelism, integer linear programming (ILP) was designed to deploy tasks on scalar processing elements (SPEs) and a vector processing element (VPE) of MIMDV. The use of a vector library for a task and the number of SPEs a task uses were determined. To reduce the overhead, synchronization is realized by barrier wait, and execution is divided into multiple time intervals called layer. We propose a novel one-step ILP that accurately minimizes the parallel time of such a situation. Furthermore, we propose a two-step ILP to achieve reasonable performance in practical time. One step is SPE mapping, and the other is layer scheduling. We tested our methods using random task graphs and real-world applications on DR1000C, a type of RISC-V MIMD processor with a vector accelerator.

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Section: A Formulation Of One-step Ilpmentioning

confidence: 99%

“…[10] parallelized blocks in function level using multi-threads. [13] partitioned the runnable graph of AMALTHEA model into tasks and then assigned the tasks to a multi-core platform. [20] introduced a tool called MiniSIGNAL generating multi-task codes from multi-layer task graphs, in which tasks are merged considering granularity.…”

Section: Related Workmentioning

confidence: 99%

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Wu,

Kumano,

Marume

et al. 2024

IEEE Access

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“…APP4MC is an open-source Eclipse platform that concentrates on performance simulation regarding mostly scheduling and timing analysis in multi-core platforms using a modelbased development approach (see Figure 6) [76,77]. The hardware and software elements can be modeled, including different properties such as the processor type, connection type among various specified modules, OS schedulers, and task properties such as execution time and deadline.…”

Section: Technologies For Software Integration and Configuration In D...mentioning

confidence: 99%

E/E Architecture Synthesis: Challenges and Technologies

Askaripoor

Farzaneh²,

Knoll

2022

Electronics

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In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driver-assisted functionalities. Consequently, a high-performance computing unit is required to provide the demanded power and process these applications while, in this case, vehicle architecture moves toward a centralized architecture. Simultaneously, appropriate software architecture has to be defined to fulfill the needs of the main computing unit and functional safety requirements. However, the process of configuring and integrating critical applications into a vehicle central computer while meeting safety requirements and optimization objectives is a time-consuming, complicated, and error-prone process. In this paper, we firstly present the evolution of the vehicle architecture, past, present, and future, and its current bottlenecks and future key technologies. Then, challenges of software configuration and mapping for automotive systems are discussed. Accordingly, mapping techniques and optimization objectives for mapping tasks to multi-core processors using design space exploration method are studied. Moreover, the current technologies and frameworks regarding the vehicle architecture synthesis, model analysis with regard to software integration and configuration, and solving the mapping problem for automotive embedded systems are expressed. Finally, we propose four research questions as future works for this field of study.

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A Concept of Vector Clock Utilization in an Iterative Tracing Approach for Distributed Embedded Systems

Cited by 2 publications

References 5 publications

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

E/E Architecture Synthesis: Challenges and Technologies

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