A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design

Wu, Hsiang-Huang; Lee, Jih-Nung; Chiang, Ming-Cheng; Liu, Po-Wei; Wu, Cheng‐Li

doi:10.1109/test.2009.5355536

Cited by 6 publications

(4 citation statements)

References 19 publications

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“…Wu et al [71] derived a new algorithm based on the steps in their study to detect these faults. The complexity of the proposed algorithm is 12N+4B+5, which is quite lower than 15N+4B+6 of the original algorithm.…”

Section: Cam Testingmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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Section: Cam Testingmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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“…We first compared the fault coverage of existing test algorithms proposed by previous researches [16][21] [18]. The fault coverage is collected with HSPICE simulations by injected all defects.…”

Section: B Fault Coverage Comparison Among Test Algorithmsmentioning

confidence: 99%

“…In the area of CAM testing, most previous researches focused on the defects locating inside CAM cells, including the symmetrical cells [14][15] [16] [17] [18] and the asymmetrical cells [19][20] [21]. [14] discussed the comparison faults which are based on the binary CAM fault models.…”

Section: Introductionmentioning

confidence: 99%

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Testing methods for quaternary content addressable memory using charge-sharing sensing scheme

Yang

Huang

et al. 2015

2015 IEEE International Test Conference (ITC)

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Due to its capability of parallel search, content addressable memory (CAM) has been widely used on the applications requiring high-speed data search. In recent years, the architectures and design techniques for CAM have been consistently evolving. However, the incoming testing issues for those newly evolved CAM designs are not fully discussed. In this paper, we investigate the testing issues for a new 28nm quaternary CAM, which provides the additional fourth state compared to a conventional ternary CAM and utilizes a charge-sharing sensing scheme for reducing its search power consumption. We first identify the new fault models for this quaternary CAM that are not covered in the conventional CAM testing based on the simulation result, and derive the corresponding test algorithm for those new fault models. The effectiveness of the proposed test algorithm is then validated by the testing result of 7200 28nm sample chips covering different process corners with the help of a newly designed command-based memory BIST.

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Path-Delay Fault Testing in Embedded Content Addressable Memories

Manikandan

Larsen

Einar

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design

Cited by 6 publications

References 19 publications

Testing nanometer memories: a review of architectures, applications, and challenges

Testing nanometer memories: a review of architectures, applications, and challenges

Testing methods for quaternary content addressable memory using charge-sharing sensing scheme

Path-Delay Fault Testing in Embedded Content Addressable Memories

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