A Comprehensive System-on-Chip Logic Diagnosis

2019 IEEE 25th International Symposium on on-Line Testing and Robust System Design (IOLTS)

et al. 2019

Self Cite

In critical (e.g. automotive) applications, Systems-on-Chip (SoC) failures that occurred during mission mode (in the field) are the most critical since they may lead to catastrophic effects. In this context, diagnosis is crucial in order to establish the root cause of observed failures with the best accuracy. With the advent of very deep submicron technologies (i.e. 7 nm), achieving such level of accuracy will become more and more difficult with today's intra-cell diagnosis tools based on effectcause or cause-effect paradigms. This will compromise the success of subsequent Physical Failure Analysis (PFA) done on defective SoCs. Machine Learning (ML) is now used in numerous classification problems where the knowledge on some data can be used to classify a new instance of such data. In particular, several ML-based solutions exist to address volume diagnosis for yield improvement. These learning-guided diagnosis approaches start from an existing set of defect candidates and try to minimize this set (eliminate bad candidates) owing to the use of ML tools and numerous data collected during production test (e.g. thousands of failed chips with candidates correctly labeled). Although efficient in volume diagnosis, these approaches cannot be used to identify the root cause of failures in customer returns, since only one failed chip is investigated in this case, with no information about the defective behavior of some other similar chips used in the same conditions (environment, workload, etc.). In this paper, we propose a new learning-guided approach for diagnosis of mission mode failures in customer returns. The proposed approach directly produces a minimum set of good candidates derived from the application of the learning-guided intra-cell diagnosis flow. Results obtained on a set of benchmark circuits, and comparison with a commercial intra-cell diagnosis tool, show the feasibility, effectiveness and accuracy of the proposed approach.

Section: Discussionmentioning

confidence: 99%

Section: State Of the Art And Motivationsmentioning

confidence: 99%

Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip

2019 IEEE 25th International Symposium on on-Line Testing and Robust System Design (IOLTS)

et al. 2019

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“…Except industrial in-house SoC diagnosis tools, very few comprehensive diagnosis approach able to deal with a full SoC and providing reliable information about fault localization exist. To the best of our knowledge, the only work targeting SoC-level diagnosis is reported in [6]. The key concept is that diagnosis consists in a comparison between a set of precomputed SoC failures and the set of failures observed during test.…”

Section: State Of the Art And Motivationsmentioning

confidence: 99%

“…This type of approach was formerly proposed in [7] and [8] but only for full-scan circuits. In [6], authors propose to extend it to the case of SoC. The main advantages of this approach w.r.t.…”

Section: State Of the Art And Motivationsmentioning

confidence: 99%

Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised Learning

IEEE Trans. Device Mater. Relib.

et al. 2020

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“…Each routine corresponds to the application of a diagnosis algorithm at a given hierarchy level. SoC level diagnosis is the first routine used to identify the core(s) in the SoC that can explain the failure [3]. Core level diagnosis (inter-cell diagnosis) is then used to identify the possible failing cells within the core(s) [4].…”

Section: Introductionmentioning

confidence: 99%

Learning-Based Cell-Aware Defect Diagnosis of Customer Returns

2020 IEEE European Test Symposium (ETS)

et al. 2020

Self Cite

In this paper, we propose a new framework for cellaware defect diagnosis of customer returns based on supervised learning. The proposed method comprehensively deals with static and dynamic defects that may occur in real circuits. A Naive Bayes classifier is used to precisely identify defect candidates. Results obtained on benchmark circuits, and comparison with a commercial cell-aware diagnosis tool, demonstrate the efficiency of the proposed approach in terms of accuracy and resolution.