A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology

Abstract

A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L e of 0.19 m, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/m at 2.9 V have been achieved.

Detecting signal-overshoots for reliability analysis in high-speed system-on-chips

“…The impact of overshoots on device hot carrier reliability and delay are also addressed in [8], [11], [12]. To reduce the effect of hot carriers in deep-submicron devices, a hybrid junction was proposed in [20] to optimize the structure in terms of performance, reliability, and manufacturability. The BERT simulator [21] analyzes hot-electron degradation in MOSFET, bipolar, and BiCMOS transistors, and predicts circuit failure-rates due to oxide breakdown and electromigration.…”

Vertical channel nMOSFET with an asymmetric graded lightly doped drain

“…However, it might degrade the device driving capability due to the large series resistance existing in the LDD regions. Improved drain-engineered MOSFET -the graded LDD (GLDD) structure has been reported in planar devices [1][2][3]. It can achieve better short channel effects immunity and hot carrier reliability due to the remarkably reduced peak electric field near the drain junction.…”

“…But in these planar GLDD devices, there are several disadvantages. Firstly, complicated technique, such as large angle oblique rotating ion implantation [1] or hybrid arsenic/ phosphorus graded n-junction [2,3], is needed for the structure realization. Secondly, the lateral GLDD profile is very difficult to be controlled and measured [4].…”

“…Secondly, the lateral GLDD profile is very difficult to be controlled and measured [4]. Thirdly, a high parasitical series resistance still exists on the source side of channel for the symmetric fabrication [1][2][3].…”

“…This vertical AGLDD device has the same advantages as the planar GLDD devices. Compared with planar GLDD structure [1][2][3], vertical AGLDD structure can be fabricated much easier and the vertical AGLDD profiles are more convenient to be controlled and measured. Furthermore, due to the asymmetric structure [5], which can also be easily realized in vertical structure, the source parasitical series resistance can be greatly reduced.…”