A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC

Appello, D.; Bernardi, P.; Giacopelli, Giuseppe; Motta, A.; Pagani, Alberto; Pollaccia, G.; Rabbi, C.; Restifo, Marco; Ruberg, P.; Sánchez, Ernesto; Villa, Claudio Maria; Venini, Federico

doi:10.23919/date.2017.7927068

Cited by 19 publications

(4 citation statements)

References 10 publications

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“…For example, this is true for the single point extended (or full) analysis, for which not only the final file may be huge, but it is usually impossible to store all intermediate information in the central memory. Consequently, processing a VCD file may require enormous resources [16], [17], i.e., computation servers with high memory capacity, and it may imply very long waiting times. A more accurate analysis of the existing applications processing VCD files showed that computation costs often depend on I/O operations, i.e., the ones required to read the input files and store the final result on the external memory unit.…”

Section: Our Methodologymentioning

confidence: 99%

Parallel Multithread Analysis of Extremely Large Simulation Traces

Appello,

Bernardi,

Calabrese

et al. 2022

IEEE Access

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With the explosion in the size of off-the-shelf integrated circuits and the advent of novel techniques related to failure modes, commercial Automatic Test Pattern Generator and fault simulation engines are often insufficient to measure the coverage of particular metrics. Consequently, a general working framework consists of storing simulation traces during the analysis phase and collecting test statistics from post-processing. Unfortunately, typical simulation traces can be hundreds of gigabytes long, and their analysis can require several days, even on large and powerful computational servers. In this paper, we propose a set of strategies to mitigate the evaluation time and the memory needed to analyze huge dump files stored in the standard Value Change Dump format. We concentrate on burn-in-related metrics that current commercial fault simulators and Automatic Test Pattern Generators cannot evaluate. We show how to divide the analysis process into several concurrent pipeline stages. We revise the logic process of each stage and all principal intermediate data structures, to adopt smart parallelization with very low contention and extremely low overhead. We exploit several low-level optimizations from modern programming techniques to reduce computation time and balance the different pipeline phases. We analyze simulation traces up to almost 250 GBytes computing different testing metrics. Overall, we can keep under control the memory usage, and we show time improvements of over two orders of magnitude compared to previously adopted state-of-the-art tools.

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Section: Our Methodologymentioning

confidence: 99%

Parallel Multithread Analysis of Extremely Large Simulation Traces

Appello,

Bernardi,

Calabrese

et al. 2022

IEEE Access

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show abstract

“…Thermal measurement on physical samples like in [28] is an important practice to also provide physical findings about the implemented SLT workload. Warming up the silicon surface of a device is often asking quite a long time (up to minutes) before the circuit shows the desired (usually high) temperatures.…”

Section: Slt Program Generationmentioning

confidence: 99%

Exploring the Mysteries of System-Level Test

Polian,

Anders,

Becker

et al. 2021

Preprint

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System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

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“…Dynamic Burn-In procedures are composed of a stress phase, which targets latent faults, and a test phase that detects the spotted faults. The most relevant stress factors in this phase are circuit activity, chip surface temperature, and current consumption [2]. It is worth mentioning that applying higher supply voltages than the nominal also accelerates the dynamic Burn-In [9].…”

Section: Test-during-burn-in Flowmentioning

confidence: 99%

“…Stress on microprocessor targets the ageing of all logic components of a CPU based system; ageing on RAM is accelerated by a specific amount of high-voltage read and write operations, while erase and verify operations are used for Flash memories. Generally, internal stress procedures induce junction level stress [2] by making the circuit toggling and thus raising the internal temperature. In this way, the internal stress complements the external acceleration factor obtained by applying high temperatures.…”

Section: Introductionmentioning

confidence: 99%

An Optimized Test During Burn-In for Automotive SoC

et al. 2018

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The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoCs). This paper proposes an optimized Test-During-Burn-In (TDBI) flow that takes advantage of the parallel execution of several types of stress procedures in which many components are carefully interleaved.The proposed methodology permits to significantly reduce the BI time and enables production monitoring by providing detailed test data-logging capabilities helping the debug of potential yield issues largely caused by the ageing of Burn-In tester consumable parts. The paper describes an experimental scenario about TDBI of an automotive SoC manufactured by STMicroelectronics.

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A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC

Cited by 19 publications

References 10 publications

Parallel Multithread Analysis of Extremely Large Simulation Traces

Parallel Multithread Analysis of Extremely Large Simulation Traces

Exploring the Mysteries of System-Level Test

An Optimized Test During Burn-In for Automotive SoC

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