A Comprehensive Evaluation of the Effects of Input Data on the Resilience of GPU Applications

Previlon, Fritz; Kalra, Charu; Kaeli, David; Rech, Paolo

doi:10.1109/dft.2019.8875269

Cited by 10 publications

(4 citation statements)

References 23 publications

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“…In detailed terms, we employed three types of tiles: random (R) tiles with a random distribution of values, zero (Z) tiles with numbers close to zero, and triangular (T) tiles with a triangular distribution of values. This selection is also in concordance with other works in the field that have argued that fault propagation in the GPU's data path is data-independent if the input data (tiles) are not biased (i.e., composed of an excessive amount of 0 s or all 1 s) [59].…”

Section: Fault Evaluation and Error Propagationsupporting

confidence: 88%

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Limas Sierra,

Guerrero-Balaguera,

Condia

et al. 2024

Electronics

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The most recent generations of graphics processing units (GPUs) boost the execution of convolutional operations required by machine learning applications by resorting to specialized and efficient in-chip accelerators (Tensor Core Units or TCUs) that operate on matrix multiplication tiles. Unfortunately, modern cutting-edge semiconductor technologies are increasingly prone to hardware defects, and the trend to highly stress TCUs during the execution of safety-critical and high-performance computing (HPC) applications increases the likelihood of TCUs producing different kinds of failures. In fact, the intrinsic resiliency to hardware faults of arithmetic units plays a crucial role in safety-critical applications using GPUs (e.g., in automotive, space, and autonomous robotics). Recently, new arithmetic formats have been proposed, particularly those suited to neural network execution. However, the reliability characterization of TCUs supporting different arithmetic formats was still lacking. In this work, we quantitatively assessed the impact of hardware faults in TCU structures while employing two distinct formats (floating-point and posit) and using two different configurations (16 and 32 bits) to represent real numbers. For the experimental evaluation, we resorted to an architectural description of a TCU core (PyOpenTCU) and performed 120 fault simulation campaigns, injecting around 200,000 faults per campaign and requiring around 32 days of computation. Our results demonstrate that the posit format of TCUs is less affected by faults than the floating-point one (by up to three orders of magnitude for 16 bits and up to twenty orders for 32 bits). We also identified the most sensible fault locations (i.e., those that produce the largest errors), thus paving the way to adopting smart hardening solutions.

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Section: Fault Evaluation and Error Propagationsupporting

confidence: 88%

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Limas Sierra,

Guerrero-Balaguera,

Condia

et al. 2024

Electronics

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“…Oliveira et al [140] provide an extensive description of software mitigation techniques for non-safety-related uses of GPUs. In addition to this, there is a reported correlation between the measured reliability and the executed applications [63,78,159], and even the explored application input sizes and biased input values [158,159] (e.g., 30% failure rate increase with input size change [159]).…”

Section: Software-only Techniquesmentioning

confidence: 89%

“…-Detection and fault-tolerance algorithmic approaches [35,138,169,170,168,195,140,49,50,110,139,156,102,202,80,204,58,76] -Fault-tolerance based on intrinsic application and/or input data characteristics [63,78,159,158] §4…”

Section: Random Hw Failuresmentioning

confidence: 99%

GPU Devices for Safety-Critical Systems: A Survey

et al. 2022

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Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance safety-critical systems such as autonomous driving systems. However, the integration of complex, parallel and computationally demanding software functions with different safety-criticality levels on GPU devices with shared hardware resources contributes to several safety certification challenges. This survey categorizes and provides an overview of research contributions that address GPU devices’ random hardware failures, systematic failures and independence of execution.

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“…Other works [8], [19] evaluated the reliability of GPUs by performing extensive fault campaigns at two abstraction levels (application and architectural). The application analysis provides some details about the vulnerability of a GPU without direct correlation with the fault effect caused in internal modules.…”

Section: A Methodologies For Reliability Evaluationmentioning

confidence: 99%

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

Condia

Rech

Santos

et al. 2022

IEEE Trans. Device Mater. Relib.

Self Cite

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Graphics Processing Units (GPUs) are increasingly adopted in several domains where reliability is fundamental, such as self-driving cars and autonomous systems. Unfortunately, GPU devices have been shown to have a high error rate, while the constraints imposed by real-time safety-critical applications make traditional (and costly) replication-based hardening solutions inadequate.This work proposes an effective methodology to identify the architectural vulnerable sites in GPUs modules, i.e. the locations that, if corrupted, most affect the correct instructions execution. We first identify, through an innovative method based on Register-Transfer Level (RTL) fault injection experiments, the architectural vulnerabilities of a GPU model. Then, we mitigate the fault impact via selective hardening applied to the flip-flops that have been identified as critical. We evaluate three hardening strategies: Triple Modular Redundancy (TMR), Triple Modular Redundancy against SETs (∆TMR), and Dual Interlocked Storage Cells (Dice flip-flops). The results gathered on a publicly available GPU Model (FlexGripPlus) considering functional units, pipeline registers, and warp scheduler controller show that our method can tolerate from 85% to 99% of faults in the pipeline registers, from 50% to 100% of faults in the functional units and up to 10% of faults in the warp scheduler, with a reduced hardware overhead (in the range of 58 % to 94% when compared with traditional TMR).Finally, we adapt the methodology to perform a complementary evaluation targeting permanent faults and identify critical sites prone to propagate fault effects across the GPU. We found that a considerable percentage (65% to 98%) of flip-flops that are critical for transient faults are also critical for permanent faults.

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A Comprehensive Evaluation of the Effects of Input Data on the Resilience of GPU Applications

Cited by 10 publications

References 23 publications

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

GPU Devices for Safety-Critical Systems: A Survey

An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs

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