A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

Goel, Nilesh; Mukhopadhyay, Subhadeep; Nanaware, N.; De, Sandip; Pandey, Rajan K.; Murali, K. V. R. M.; Mahapatra, S.

doi:10.1109/irps.2014.6861100

Cited by 29 publications

(16 citation statements)

References 36 publications

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“…1, PBTI remained negligible for SiON n-MOSFETs and became important with the introduction of HKMG technology [36]. As mentioned before, NBTI in HKMG MOSFETs results in positive charge buildup in the SiO 2 or SiON IL due to trap generation at Si/IL interface and hole trapping in IL bulk [16,17,34]. In contrast, PBTI results in negative charge buildup in HfO 2 High-K layer as shown in Fig.…”

Section: Introductionmentioning

confidence: 91%

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Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Mukhopadhyay

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

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In this chapter, direct characterization techniques have been used to access the trap generation and trapping subcomponents of BTI degradation in HKMG MOSFETs having different gate stack processes. Generation of new traps is estimated using DCIV for NBTI stress and both DCIV and SILC for PBTI stress respectively in p-and n-channel MOSFETs. Flicker noise is used to estimate the density of process related pre-existing gate insulator traps responsible for hole and electron trapping respectively during NBTI and PBTI stress. The spatial and energetic locations of generated traps for NBTI and PBTI stress are identified. The time, bias, and temperature dependencies of trap generation obtained using the DCIV technique are compared between NBTI and PBTI stress, while these parameters obtained using DCIV and SILC techniques are compared for PBTI stress. The relative dominance of trap generation and trapping on NBTI and PBTI threshold voltage degradation is estimated for different gate insulator processes. IntroductionFrom a practical point of view of technology qualification, it is important to know the magnitude of Bias Temperature Instability (BTI) at end-of-life of devices and hence of circuits and products under normal use condition. Estimation of Negative BTI (NBTI) and Positive BTI (PBTI) respectively in p-and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is usually done by stressing the devices at higher than normal gate bias (V G = V G-STR ) and measuring the resulting device parametric degradation with minimal impact of recovery artifacts. Different "recovery-free" measurement techniques have been discussed in Chap. 2. As mentioned before, stress tests are usually performed for few hours or

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Section: Introductionmentioning

confidence: 91%

“…Furthermore, trap generation (ΔN OT ) in bulk IL also contributes for situations involving high stress gate bias (V G-STR ). Mutually uncoupled ΔN IT and ΔN HT (and also ΔN OT for certain situations) mechanisms can explain different gate insulator process dependent NBTI data [5,[33][34][35], and is discussed later in Chap. 4.…”

Section: Introductionmentioning

confidence: 99%

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Mukhopadhyay

Mahapatra

2015

Fundamentals of Bias Temperature Instability in MOS Transistors

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“…NBTI in HKMG p-FETs was studied using mutually uncorrelated components of trap generation at Si/IL interface and IL/HK interface and hole trapping into pre-existing IL traps [21]. It is important to study impact of NBTI on circuits like SRAM cell, Ring-Oscillator (RO) and digital logic gates.…”

Section: Introductionmentioning

confidence: 99%

“…So, becomes inaccessible in subsequent stress phase or next on-cycle of AC stress. This we call trap disappear by electron occupancy [21].…”

Section: Introductionmentioning

confidence: 99%

“…f is occupancy factor [18], [21] 'V T = Gamma ((PV) 2 , V P V = K TECH (P To perform circuit level Monte-Carlo simulations we need suitable compact model, which incorporate occupancy and can gave us ΔVT mean for both DC and AC stress at different time, duty factor and frequency [18]. Note that experimental results and numerical simulation shows that NBTI degradation is independent to AC frequency, but it has characteristic shape for AC stress at different duty factor [21].…”

Section: Introductionmentioning

confidence: 99%

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Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages

Goel

Dubey²,

Kawa

et al. 2015

2015 IEEE International Reliability Physics Symposium

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BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20nm FinFET for two types of 6T SRAM cells, HighSpeed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of VDD reduction on timezero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified.

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Fundamentals of Bias Temperature Instability in MOS Transistors

Mahapatra¹

2016

Springer Series in Advanced Microelectronics

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The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series forms a bridge between physics and engineering and the volumes will appeal to practicing engineers as well as research scientists.More information about this series at

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A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

Cited by 29 publications

References 36 publications

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages

Fundamentals of Bias Temperature Instability in MOS Transistors

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