A Comprehensive Analytical Performance Model of DRAM Caches

Abstract

Stacked DRAM promises to offer unprecedented capacity, and bandwidth to multi-core processors at moderately lower latency than off-chip DRAMs. A typical use of this abundant DRAM is as a large last level cache. Prior research works are divided on how to organize this cache and the proposed organizations fall into one of two categories: (i) as a Tags-In-DRAM organization with the cache organized as small blocks (typically 64B) and metadata (tags, valid, dirty, recency and coherence bits) stored in DRAM, and (ii) as a Tags-In-SRAM organization with the cache organized as larger blocks (typiclly 512B or larger) and metadata stored on SRAM. Tags-In-DRAM organizations tend to incur higher latency but conserve off-chip bandwidth while the Tags-In-SRAM organizations incur lower latency at some additional bandwidth. In this work, we develop a unified performance model of the DRAM-Cache that models these different organizational styles. The model is validated against detailed architecture simulations and shown to have latency estimation errors of 10.7% and 8.8% on average in 4-core and 8core processors respectively. We also explore two insights from the model: (i) the need for achieving very high hit rates in the metadata cache/predictor (commonly employed in the Tags-In-DRAM designs) in reducing latency, and (ii) opportunities for reducing latency by load-balancing the DRAM Cache and main memory.

A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5

“…Most of the prior research work in DRAM cache organization do not provide detailed methodologies required to model a DRAM cache during the simulation. In terms of modeling of a DRAM cache, Gulur et al [21] presented an analytical performance model of DRAM cache for in-SRAM and in-DRAM tag storage organizations. Their model considers parameters such as DRAM Cache's and off-chip memory's timing values, cache block size, tag cache/predictor hit rate and workload characteristic, to estimate average miss penalty and bandwidth seen by the last level on chip SRAM cache (LLSC).…”

Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems

“…In addition to simulation methodologies, some work exists on using analytical models for DRAM caches. For example, Gulur et al [36] presented an analytical performance model of different DRAM organizations. However, their work is agnostic to the micro-architectural and timing constraints of main memory technologies cooperating with DRAM cache, and still leaves a gap for a full system DRAM cache simulation for detailed architectural analysis.…”