A complete scheme of built-in self-tests (BIST) structure for fault diagnosis in analog circuits and systems

Hatzopoulos, A.A.; Siskos, S.; Kontoleon, J.M.

doi:10.1109/19.231591

Cited by 20 publications

(2 citation statements)

References 7 publications

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“…A memory BIST that is based on error detecting codes is described in [6]. BIST and diagnosis of analog circuits is described in [5]. BIST for static RAMs is described in [13].…”

Section: Introductionmentioning

confidence: 99%

BIST‐Based Fault Diagnosis in the Presence of Embedded Memories

Savir

2000

VLSI Design

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An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

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“…A memory BIST that is based on error detecting codes is described in [6]. BIST and diagnosis of analog circuits is described in [5]. BIST for static RAMs is described in [13].…”

Section: Introductionmentioning

confidence: 99%

BIST‐Based Fault Diagnosis in the Presence of Embedded Memories

Savir

2000

VLSI Design

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“…The difficulties of testing such systems arises from the limited observability and controllability of internal circuit structures, along with the non-linear effect that analog faults may cause on a circuit [4,5,6]. Much research is currently addressing the observability and controllability problems by providing test structures on chip, i.e., the Built-In Self-Test (BIST) approach [7,8,9,10,111. In conjunction with analog BIST, work is also directed at the identification problem [12,13,14, 151, i.e., identifying the presence of faulty components in a network.…”

Section: : Introductionmentioning

confidence: 99%

On the testability of CMOS feedback amplifiers

Bishop

Ivanov²

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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This paper examines the testability of a CMOS operational amplifier (op-amp) in four different feedback configurations. Feedback is often considered to complicate the testing problem. Here, we illustrate that it is possible to test the op-amp for catastrophic faults at wafer probe without having to remove feedback structures. Catastrophic, as well as parameter variation fault models, are used to simulate the faulty response of the opamp circuits. OUT method relies on repeated Monte Carlo fault simulations to examine differences in a circuit's response for each possible fault condition. A sine wave is used for the test stimulus in each case. FOUT closed loop configurations are considered for the study: integrator, differentiator, inverting amplifier, and comparator. w e tally the percentage of stuck-at, short, and open faults that are detectable with the feedback applied to demonstrate that the four feedback network configurations have little effect on the catastrophic fault coverage, as compared with similar tests performed for an open-loop configuration [I].

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Ultra-Low Power Application-Specific Integrated Circuits for Sensing

Kassanos

Yang

2018

Implantable Sensors and Systems

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A complete scheme of built-in self-tests (BIST) structure for fault diagnosis in analog circuits and systems

Cited by 20 publications

References 7 publications

BIST‐Based Fault Diagnosis in the Presence of Embedded Memories

BIST‐Based Fault Diagnosis in the Presence of Embedded Memories

On the testability of CMOS feedback amplifiers

Ultra-Low Power Application-Specific Integrated Circuits for Sensing

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