A complete data scheduler for multi-context reconfigurable architectures

Sánchez-Élez, M.; Fernández, M.; Maestre, Rafael; Hermida, R.; Bagherzadeh, Nader; Kurdahi, Fadi

doi:10.1109/date.2002.998354

Cited by 10 publications

(7 citation statements)

References 8 publications

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“…However, the paper only considers statically configurable logic, and does not consider run-time reconfigurable architectures. A different approach for coarsegrained reconfigurable computing is presented in [10]. In the paper, a data scheduler algorithm is proposed to reduce the overall system energy.…”

Section: Related Workmentioning

confidence: 99%

Power-performance trade-offs for reconfigurable computing

Noguera

Badía

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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In this paper, we explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. We show that an efficient hardware-software partitioning algorithm is required when targeting low-power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. This work presents a configurationaware data size partitioning approach. We propose a design methodology that adapts the architecture and used algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

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Section: Related Workmentioning

confidence: 99%

Power-performance trade-offs for reconfigurable computing

Noguera

Badía

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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“…Additional techniques are given in [18] and [20]. A technique for application partitioning between configurable logic and an embedded processor is given in [20].…”

Section: Previous Workmentioning

confidence: 99%

System-level power-performance tradeoffs for reconfigurable computing

Noguera

Badía

2006

IEEE Trans. VLSI Syst.

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In this paper, we propose a configuration-aware datapartitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.Index Terms-Hardware/software (HW/SW) codesign, powerperformance tradeoffs, reconfigurable computing (RC).

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“…The static implementation of an application is separated in two or more independent hardware contexts, which may be swapped during runtime [2]. Extensive work was done to improve the multi-context handling capability of these devices, by storing several configurations and enabling quick context switching [3], [4]. The main goal was to improve the execution time by minimizing external memory transfers, assuming that some amount of on-chip data storage was available in the reconfigurable architecture.…”

Section: Introductionmentioning

confidence: 99%

Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution

Gericota

Alves

Silva

et al. 2008

IEEE Trans. VLSI Syst.

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Abstract-Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

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A complete data scheduler for multi-context reconfigurable architectures

Cited by 10 publications

References 8 publications

Power-performance trade-offs for reconfigurable computing

Power-performance trade-offs for reconfigurable computing

System-level power-performance tradeoffs for reconfigurable computing

Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution

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