A compilation technique for software pipelining of loops with conditional jumps

Abstract

We describe a compilation algorithm for efficient software pipelining of general inner loops, where the number of iterations and the time taken by each iteration may be unpredictable, due to arbitrary if-then-else statements and conditional exit statements within the loop. As our target machine, we assume a wide instruction word architecture that allows multi-way branching in the form of if-then-else trees, and that allows conditional register transfers depending on where the microinstruction branches to (a hardware implementation proposal for such a machine is briefly described in the paper). Our compilation algorithm, which we call the pipeline scheduling technique, produces a software-pipelined version of a given inner loop, which allows a new iteration of the loop to begin on every cycle whenever dependences and resources permit. The correctness and termination properties of the algorithm are studied in the paper.

A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows

“…As a specific example architecture, we use the tree VLIW architecture model [3,15], which satisfies the architectural requirements described above. In this architecture, a parallel VLIW instruction, called a tree instruction, is represented by a binary decision tree as shown in Fig.…”

“…Formally, the first constraint on transformations can be given as follows. Second, the final store 3 of p e,sp should be equal to that of p e to preserve the semantic of L. For this, we require that for any node n = node(n), where n is a node instance in t(p e ), if the target register of n is live at the exit of p e , the value defined by node(sp ni p e ,p e,sp (n)) should be eventually committed to reg W (n) along p e,sp . For simplicity, we assume that all registers in p e are regarded as being live at the exit of p e during software pipelining.…”

“…Although there were several related research investigations [2,3,4] on the problem of time optimal software pipelining of loops with control flows, there have been few significant theoretical results published. The work by Schwiegelshohn et al [1] is the best known and most significant result so far, which simply illustrated that, for some loops with control flows, there cannot exist time optimal parallel programs.…”

“…In fact, most complications of the nonexistence proof in Sect. 6 as well as the formalization of software pipelining are due to expanded solution space opened up by branch reordering transformation 3. Temporary registers are excluded.…”

Software pipelining: an effective scheduling technique for VLIW machines

“…The software pipelining algorithms proposed by Su et al [27.28], and Aiken and Nicolau [l], assume that the schedules for the iterations are given and cannot be changed. Ebcioglu proposed a software pipelining algorithm to generate code for a hypothetical machine with infinitely many hardware resouruzs [7]. Lastly, Weiss and Smith compared the results of using loop unrolling and software pipelining to generate scalar code for the Cray-1s architecture [31].…”