A comparison of embedded and non-embedded FPGA implementations for fractional chaos-based random number generators

Clemente-López, Daniel; Rangel-Magdaleno, José; Muñoz‐Pacheco, Jesús M.; Morales-Velazquez, Luis

doi:10.1007/s12652-022-04382-y

Cited by 5 publications

(2 citation statements)

References 46 publications

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“…The board is equipped with a low-cost Spartan 6 XC6SLX45 FPGA with a clock frequency of 48 MHz; it also features static random-access memory (RAM), communication ports such as the universal serial bus (USB), and universal asynchronous receiver transmitter (UART), power management, and flash memory. A 16-bit xQuP01v0 processor is embedded in the FPGA, besides an interconnection in-system bus (ISB), both proprietary designs; a broader description of the applications of the FPGA-based proprietary board can be found in [51,52]. The input data used in the system is scaled to an input range of [−2, 2), and signal data are converted to a binary stream in 2.14 fixed-point format saved in onboard flash memory.…”

Section: -Bit Upmentioning

confidence: 99%

FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots

2023

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Industrial processes involving manipulator robots require accurate positioning and orienting for high-quality results. Any decrease in positional accuracy can result in resource wastage. Machine learning methodologies have been proposed to analyze failures and wear in electronic and mechanical components, affecting positional accuracy. These methods are typically implemented in software for offline analysis. In this regard, this work proposes a methodology for detecting a positional deviation in the robot’s joints and its implementation in a digital system of proprietary design based on a field-programmable gate array (FPGA) equipped with several developed intellectual property cores (IPcores). The method implemented in FPGA consists of the analysis of current signals from a UR5 robot using discrete wavelet transform (DWT), statistical indicators, and a neural network classifier. IPcores are developed and tested with synthetic current signals, and their effectiveness is validated using a real robot dataset. The results show that the system can classify the synthetic robot signals for joints two and three with 97% accuracy and the real robot signals for joints five and six with 100% accuracy. This system aims to be a high-speed reconfigurable tool to help detect robot precision degradation and implement timely maintenance strategies.

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Section: -Bit Upmentioning

confidence: 99%

FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots

2023

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“…The paper examines the cryptographic techniques AES, RSA, DES, 3DES, and Blowfish, as well as the steganography algorithm LSB. The cryptographic algorithms are Java programmers that have been imported into the MATLAB environment (Clemente-López et al, 2024;Kaur & Kaur, 2021). An investigation is done on the mentioned algorithms at the same time and same environment to contrast the discrete factors such as encryption and decryption timespan, SNR, Histogram and MSE (Markus & Kertesz, 2020).…”

Section: Introductionmentioning

confidence: 99%

Enhancing Security through Advanced Image Steganography Techniques

BHATT,

PARGI,

KUMAR

2024

OPSearch

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The project aims to explore various types of steganography techniques, with a focus on image steganography, where information is concealed within images. This involves decrypting the hidden data to retrieve the message image, a process that can be achieved through different methods. The study delves into image steganography, which involves hiding information such as text, images, or audio files within other image or video files. Specifically, the project concentrates on utilizing steganography to embed an image within another image using spatial domain techniques. By examining this particular method, the project seeks to deepen understanding of how image steganography operates and its potential applications. This research contributes to the field by providing insights into the implementation and effectiveness of steganography techniques, offering valuable knowledge for information security and data protection purposes. Through practical demonstrations and analysis, the project aims to showcase the capabilities and limitations of image steganography, facilitating further research and development in this domain. Ultimately, the project endeavors to enhance comprehension of steganography methods and their significance in safeguarding digital information

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FPGA Realization of Two Different Fractional- Order Time-Delay Chaotic System With Predefined Synchronization Time

Lin

Wang²,

Cai

2022

IEEE Access

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A comparison of embedded and non-embedded FPGA implementations for fractional chaos-based random number generators

Cited by 5 publications

References 46 publications

FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots

FPGA-Based Methodology for Detecting Positional Accuracy Degradation in Industrial Robots

Enhancing Security through Advanced Image Steganography Techniques

FPGA Realization of Two Different Fractional- Order Time-Delay Chaotic System With Predefined Synchronization Time

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