A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation

Thomas, David B.; Howes, Lee; Luk, Wayne

doi:10.1145/1508128.1508139

Cited by 141 publications

(85 citation statements)

References 23 publications

(34 reference statements)

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“…In the source code, flux is represented as an array with five elements, and each element can be accessed by using its number as an element, e.g. f lux 3 . Like f lux, f lux sum is a two-dimensional array for which the index indicates a vector element and a grid number.…”

Section: Target Subroutinesmentioning

confidence: 99%

“…Such data dependency reduces the computational efficiency because data must wait to be processed when they are being processed, otherwise, the results are incorrect [16]. In addition, degraded performance is also observed in other subroutines: (2) Green Gauss, (3) …”

Section: Target Subroutinesmentioning

confidence: 99%

“…However, execution on highly parallel machines efficiently is difficult because of its consecutive accesses using pointers and irregular memory access patterns caused by the unstructured mesh [1]. Since economical accelerators like GPGPU (general-purpose computing on graphics processing units) and Cell Broadband Engine rely on parallel data processing, they are not suitable for accelerating applications with complicated data dependency [2], [3]. Reconfigurable systems consisting of multiple field programmable gate arrays (FPGAs) are a promising solution to the parallel processing problem.…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

Akamine

Talip

Osana

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYComputational fluid dynamics (CFD) is an important tool for designing aircraft components. FaSTAR (Fast Aerodynamics Routines) is one of the most recent CFD packages and has various subroutines. However, its irregular and complicated data structure makes it difficult to execute FaSTAR on parallel machines due to memory access problem. The use of a reconfigurable platform based on field programmable gate arrays (FPGAs) is a promising approach to accelerating memory-bottlenecked applications like FaSTAR. However, even with hardware execution, a large number of pipeline stalls can occur due to read-after-write (RAW) data hazards. Moreover, it is difficult to predict when such stalls will occur because of the unstructured mesh used in FaSTAR. To eliminate this problem, we developed an out-of-order mechanism for permuting the data order so as to prevent RAW hazards. It uses an execution monitor and a wait buffer. The former identifies the state of the computation units, and the latter temporarily stores data to be processed in the computation units. This out-of-order mechanism can be applied to various types of computations with data dependency by changing the number of execution monitors and wait buffers in accordance with the equations used in the target computation. An out-of-order system can be reconfigured by automatic changing of the parameters. Application of the proposed mechanism to five subroutines in FaSTAR showed that its use reduces the number of stalls to less than 1% compared to without the mechanism. In-order execution was speeded up 2.6-fold and software execution was speeded up 2.9-fold using an Intel Core 2 Duo processor with a reasonable amount of overhead. key words: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, out-oforder system

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Section: Target Subroutinesmentioning

confidence: 99%

Section: Target Subroutinesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

Akamine

Talip

Osana

et al. 2014

IEICE Trans. Inf. & Syst.

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“…Both approaches are not CPU-free and the numbers are not generated on demand. GPU-based random numbers generators are discussed by Nguyen (2007) and Thomas et al (2009). Bastos-Filho et al (2010) presented a CPU-free approach for generating random numbers on demand based on the Xorshift generator (Marsaglia (2003)).…”

Section: Synchronization Barriersmentioning

confidence: 99%

Running Particle Swarm Optimization on Graphic Processing Units

Bastos-Filho¹,

Oliveira²,

Nascimento³

2011

Search Algorithms and Applications

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“…Floating-point arithmetic implementation on FPGA is inefficient for the same reason [12]. Often, a careful decision among alternative algorithms is necessary for optimal performance [7].…”

Section: A Application Domainsmentioning

confidence: 99%

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

Papakonstantinou

Gururaj

Stratton

et al. 2009

2009 IEEE 7th Symposium on Application Specific Processors

126

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Abstract-As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore's law, the computing industry has switched its route to higher performance through parallel processing. The rise of multi-core systems in all domains of computing has opened the door to heterogeneous multi-processors, where processors of different compute characteristics can be combined to effectively boost the performance per watt of different application kernels. GPUs and FPGAs are becoming very popular in PC-based heterogeneous systems for speeding up compute intensive kernels of scientific, imaging and simulation applications. GPUs can execute hundreds of concurrent threads, while FPGAs provide customized concurrency for highly parallel kernels. However, exploiting the parallelism available in these applications is often not a push-button task. Often the programmer has to expose the application's fine and coarse grained parallelism by using special APIs. CUDA is such a parallel-computing API that is driven by the GPGPU industry and is gaining significant popularity. In this work, we adapt the CUDA programming model into a new FPGA design flow called FCUDA, which efficiently maps the coarse and fine grained parallelism exposed in CUDA onto the reconfigurable fabric. Our CUDA-to-FPGA flow employs AutoPilot, an advanced high-level synthesis tool which enables high-abstraction FPGA programming. FCUDA is based on a source-to-source compilation that transforms the SPMD CUDA thread blocks into parallel C code for AutoPilot. We describe the details of our CUDA-to-FPGA flow and demonstrate the highly competitive performance of the resulting customized FPGA multi-core accelerators. To the best of our knowledge, this is the first CUDA-to-FPGA flow to demonstrate the applicability and potential advantage of using the CUDA programming model for high-performance computing in FPGAs.

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A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation

Cited by 141 publications

References 23 publications

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

Running Particle Swarm Optimization on Graphic Processing Units

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

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