A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

Keller, Matthias; Buhmann, Alexander; Sauerbrey, Jens; Ortmanns, Maurits; Manoli, Yiannos

doi:10.1109/tcsi.2008.925362

Cited by 115 publications

(52 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For instance, let us consider the excess loop delay with an amount s d = 1. According to (9), the LF when s d = 1 is And, when comparing (10) with the ideal AP case from (5), there will be one additional pole which may affect the performance of the modulator. Figure 10 exhibits the comparison of the NTF in an example of a hybrid AP modulator with a = 0.25 as in (6) with or without 1 clock cycle ELD effect.…”

Section: Loop Function Optimization With Single-bit Quantizermentioning

confidence: 99%

“…Due to ELD, when Non-Return-to-Zero (NRZ) feedback is used, a part of the feedback pulse will be shifted into the next clock cycle which may lead to system instability [4][5][6][7]. In order to reduce the serious effect of ELD in the CT DR modulator a diversified range of compensation methods have been proposed [1,[4][5][6][7][8][9], where in [10,11] the amount of the delay is larger than one clock period and it can also be compensated. However, they are applied in full-active modulators due to the lack of isolation in passive integrators [12,13].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

Cai

Yang

Sin

et al. 2013

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

The design and optimization methodology for CT RD modulators with hybrid Active-Passive (AP) loopfilters is indicated in this work. From the discussion, by appropriately scaling the passive filter gain and cooperating with a single-bit quantizer, the hybrid AP loop filtering can achieve an approximated noise-shaping function as a fully active DR modulator with the same order. The ELD effect in the hybrid AP CT DR modulator which influences the poles and zeros locations of the Noise Transfer Function (NTF) in the modulator is depicted. This paper also investigates the feasibility of applying the ELD compensation techniques that were used to be implemented in the active integrator's case to the hybrid AP CT DR modulator; however, some of them cannot be practically applied since the passive loop-filter cannot perform proportional feedback signal summation. After the discussion and analysis, the technique similar to Vadipour et al. (In: Symposium on VLSI circuits digest of technical papers, 2008) can be easily implemented at circuit-level and after applying it, there is one additional zero to compensate the peak in the NTF. With the help of this technique, the maximum quantizer delay tolerance can be a full clock period. The mentioned ELD compensation technique was applied in a 2nd order CT DR modulator with an active-RC integrator as the 1st stage and a passive RC filter as the 2nd stage, which was verified by transistor-level simulations in 65 nm CMOS. The circuit exhibits either 67.3 dB or 65.3 of SNDR, under the effect of half clock period or one clock period ELD, respectively; by contrast, without compensation, the system is unstable with both half or one clock period ELD effect. The designed hybrid CT DR modulator achieves 2 MHz signal bandwidth and consumes 2.54 mW of power.

show abstract

Section: Loop Function Optimization With Single-bit Quantizermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

Cai

Yang

Sin

et al. 2013

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Here the delay is set to half a clock cycle. This way explicit ELD is introduced, which is compensated by a direct feedback path to the input of the quantizer [1], [2], [8], [10], [13]. A current-steering feedback DAC is present, which generates a non-return-to-zero (NRZ) pulse:…”

Section: Parasitic Effects In Continuous-time σ∆ Modulatorsmentioning

confidence: 99%

“…However, it is well known that CT Σ∆ modulators are sensitive to various parasitic effects, which are much less pronounced in DT modulators. Amongst them are integrator coefficient RC variations, excess loop delay (ELD), parasitic poles and zeros in the integrator transfer functions and increased clock jitter sensitivity [8]- [11]. All these effects make that the actual implemented NTF deviates from the desired one [12].…”

Section: Introductionmentioning

confidence: 99%

A Rigorous Approach to the Robust Design of Continuous-Time $\Sigma\Delta$ Modulators

Vuyst

Rombouts

Gielen

2011

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-In this paper we present a framework for robust design of continuous-time Σ∆ modulators. The approach allows to find a modulator which maintains its performance (stability, guaranteed peak SNR, . . . ) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time Σ∆ modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behaviour of the signal transfer function can be controlled with our design framework.

show abstract

“…A well known example of undesired loop dynamics is the effect of excess loop delay (ELD) [7]. ELD models the finite decision time of a real-life quantizer.…”

Section: A Undesired Loop Dynamicsmentioning

confidence: 99%

The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time $\Sigma\Delta$ Modulators

Vuyst

Rombouts

Maeyer

et al. 2010

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Abstract-In this paper we introduce a figure of merit for the robustness of continuous-time Σ∆ modulators. It is based on the Nyquist criterion for the equivalent discrete-time (DT) loop filter. We show how continuous-time modulators can be designed by optimizing this figure of merit. This way we obtain modulators with increased robustness against variations in the noise-transfer-function (NTF) parameters. This is particularly useful for constrained systems, where the system order exceeds the number of design parameters. This situation occurs for example due to the effect of excess loop delay (ELD) or finite gain bandwidth (GBW) of the opamps.Additionally, it is shown that the optimization is equivalent to the minimization of H∞, the maximum out-of-band gain of the NTF. This explains why conventional design strategies that are based on H∞, such as Schreier's approach, provide quite robust modulator designs in the case of unconstrained architectures.

show abstract

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

Cited by 115 publications

References 15 publications

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

A Rigorous Approach to the Robust Design of Continuous-Time $\Sigma\Delta$ Modulators

The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time $\Sigma\Delta$ Modulators

Contact Info

Product

Resources

About