A Comparative Study of Surface and Buried P-Channel 0.10um MOSFETs

Abstract

This paper presents a comparison between two designs of 0.10 µm gate length pMOSFETs processed with either a surface channel (SC) p+ polysilicon gate or a buried channel (BC) n+ polysilicon gate. Except for the channel and gate architectures, the other pMOSFET design parameters such as gate oxide (2.3 nm), gate patterned with hybrid lithography, LDD structure, are similar. An analysis of both electrical performances and relevant parameters is presented. Although BC pMOSFET can be scaled down to 0.10 µm geometries with Arsenic tilted pocket, we demonstrate that the low threshold voltage (Vt) of SC pMOSFET due to better short channel effect (SCE) control, combined with p+ gate doping concentration optimisation leads to a definitive advantage of SC pMOSFET.