A Comparative Performance Analysis of 6T, 7T and 8T SRAM Cells in 18nm FinFET Technology

Kumar, Vivek; Tomar, V. K.

doi:10.1109/parc49193.2020.236620

Cited by 5 publications

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…40,41 Additionally, few simulations factors were recorded for the proposed 21T-Cell since most of the simulations had been exploited for the SRAM-based 8T-Cell in previous works. [34][35][36] Subsequently, the DC simulation measures the sensitivity operations in terms of noise margin using the butterfly input(v) versus output(v) as delineated in Table 2. Such as the characteristics of noise margin pertains to read (RNM), write (WNM), and content-address (CNM).…”

Section: Hspice Simulationsmentioning

confidence: 99%

“…Consequently, the write operation also has a superior noise margin with respect to 6T-Cell since the cross-coupled inverters are dedicated for only write operation, and thus their geometry sizes are designed for maximum butterfly shape. [34][35][36] Furthermore, the sizes of the transistors of the proposed 21T-Cell have two different values. The size of the transistors of the write circuitry is W = 180 nm/L = 180 nm, while the size of the transistors of the read and content-address circuits is W = 180 nm/L = 90 nm.…”

Section: Hspice Simulationsmentioning

confidence: 99%

“…31,32 Furthermore, the 8T-Cell facilitates design time to market by introducing an automation algorithm from schematic layout to physical layout with the support of 8T-Cell library standard cell components. 33 Recent studies investigate the 8T-Cell for ultra-low power supply applications and its sensitivity against PVT process corners and compare it with other cells structures, [34][35][36] wherein the 8T-Cell has several advantages over the counterpart cells in multiport applications. Therefore, this work considers the 8T-Cell along with the CAM structure to constitute the RRU tables, where the CAM circuitry has been added to the 8T-Cell forming a hybrid SRAM-based CAM cell structure.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of memory Alias Table based on the SRAM 8T‐Cell

Abdel‐hafeez

Otoom

Quwaider

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW.

show abstract

Section: Hspice Simulationsmentioning

confidence: 99%

Section: Hspice Simulationsmentioning

confidence: 99%