A new message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is desi ned to be a general-purpose parallel architecture suitable 8, wafer scale integration. Generalized stochastic Petri nets (GSPN) are used to model the behavior of the MMCPC. The GSPN performance modeling results show a need for a new processing element(PE). A new PE architecture, able to handle data processing and message passing concurrently, is proposed and the silicon overhead is estimated in comparison with transputer-like PE's. Based on the proposed PE, optimum sizes of the MMCPC for different program structures are derived. At last, a 2D FFT problem serves as an example to demonstrate that the MMCPC is indeed a cost-effective performance enhancement architecture to a real problem.