A Compact Implementation of Parasitic Inductance Cancellation for Shunt Capacitor Filters on Multilayer PCBs

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

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“…6. As can be seen, the admittance (2,3) and Y aux (3,2), whereas 1  cap Z is placed at Y aux (8,8).…”

Section: B External Device Modelingmentioning

confidence: 99%

An Accurate Modeling Approach to Compute Noise Transfer Gain in Complex Low Power Plane Geometries of Power Converters

Nguyen¹,

Blanchette²,

Wang³

2017

Journal of Power Electronics

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“…In [1], diagonally and shunt-connected two film capacitors called "X-capacitor-inductor structure" is reported which can be equivalently transformed by network theory into a one shunt-path circuit containing a negative inductance to cancel ESL. In [2]- [7], negative inductance is equivalently added in series to the shunt-path by magnetic coupling between various circuit components: a main line and a shunt-path [2], loops configured by via holes and lines connected to chip capacitors [3], a spiral-shaped line and a line connected to a three-terminal chip capacitor [4], vertically stacked coupled square loops [5], a chip capacitor itself and a main line [6], and a chip capacitor itself and bilateral lines adjacent to the capacitor [7].…”

Section: Introductionmentioning

confidence: 99%

“…In [2], a configuration for a single film capacitor is presented, however, coupled windings are employed those require larger area than required for vertically stacked coupled square loops in the proposed circuit. Configurations in [3]- [7] are an application for a chip capacitor connected between a single line and the GND, and so that it is not easy to apply them directly for a shunt-connected film capacitor filter.…”

Section: Introductionmentioning

confidence: 99%

An ESL-Cancelling Circuit for a Shunt-Connected Film Capacitor Filter Using Vertically Stacked Coupled Square Loops

YONEDA,

KOBAYASHI,

TANIGUCHI

2023

IEICE Trans. Commun.

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An ESL-cancelling circuit for a shunt-connected film capacitor filter using vertically stacked coupled square loops is reported in this paper. The circuit is applicable for a shunt-connected capacitor filter whose equivalent series inductance (ESL) of the shunt-path causes deterioration of filter performance at frequencies above the self-resonant frequency. Two pairs of vertically stacked magnetically coupled square loops are used in the circuit those can equivalently add negative inductance in series to the shunt-path to cancel ESL for improvement of the filter performance. The ESL-cancelling circuit for a 1-µF film capacitor was designed according to the Biot-Savart law and electromagnetic (EM)-analysis, and the prototype was fabricated with an FR4 substrate. The measured result showed 20-dB improvement of the filter performance above the selfresonant frequency as designed, satisfying S dd21 less than −40 dB at 1 MHz to 100 MHz. This result is almost equivalent to reduce ESL of the shuntpath to less than 1 nH at 100 MHz and is also difficult to realize using any kind of a single bulky film capacitor without cancelling ESL.

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Current imbalance analysis of multichip influenced by parasitic inductance within PP-IEGT

Wang,

Dai,

Zhao

et al. 2024

Microelectronics Reliability

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A Compact Implementation of Parasitic Inductance Cancellation for Shunt Capacitor Filters on Multilayer PCBs

Cited by 11 publications

References 11 publications

An Accurate Modeling Approach to Compute Noise Transfer Gain in Complex Low Power Plane Geometries of Power Converters

An Accurate Modeling Approach to Compute Noise Transfer Gain in Complex Low Power Plane Geometries of Power Converters

An ESL-Cancelling Circuit for a Shunt-Connected Film Capacitor Filter Using Vertically Stacked Coupled Square Loops

Current imbalance analysis of multichip influenced by parasitic inductance within PP-IEGT

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